FPGA USB Interface Using Oversampling Without CDR
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Solution Overview
Problem
Conventional FPGAs face challenges in handling high-speed USB 2.0 modes due to limitations in device connectivity and the need for additional circuits like CDR for proper data transmission.
Innovation Solution
The system incorporates a USB interface with differential comparators to identify logic zero states and a method for high-speed data communication that involves oversampling data signals using clock signals twice as fast as the data rate, with a 90-degree phase shift, to facilitate transmission on P-channel and N-channel buses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional FPGA uses GPIO to handle USB low-speed and full-speed modes, then it can maintain simplicity, but it cannot handle USB 2.0 high-speed mode effectively
Solution Approach 1:
The USB interface is designed to handle multiple USB speed modes (low-speed, full-speed, and high-speed) through a unified architecture. The same interface infrastructure supports all three modes by dynamically adjusting operational parameters rather than requiring separate dedicated interfaces for each mode, thereby achieving multi-functionality without proportionally increasing complexity.
Solution Approach 2:
The interface employs dynamic clocking and data rate adjustment mechanisms that allow the FPGA to adapt its operational characteristics based on the detected USB mode. The system can dynamically switch between different data rates and timing parameters, enabling the same hardware to optimize its performance for each specific USB speed mode without being locked into a fixed configuration.
2Speed
If FPGA deploys CDR circuit and serdes to handle USB 2.0 high-speed mode, then it can achieve high-speed communication, but it increases device complexity and resource consumption
Solution Approach 1:
The invention extracts and removes the CDR (Clock Data Recovery) circuit from the required component list. By using a simplified sampling approach with phase-shifted clocks directly generated within the FPGA, the patent eliminates the need for external or complex integrated CDR circuits, thereby achieving high-speed communication without the associated complexity and resource overhead.
Solution Approach 2:
The patent uses a simplified clocking scheme that replicates the function of CDR through phase-shifted clock copies. Instead of implementing complex phase-locked loops and data recovery circuits, the system creates multiple copies of the clock signal with different phases (0°, 90°, 180°, 270°) and uses these to sample the data stream, achieving equivalent functionality through a simpler mechanism.
3Device complexity
If FPGA uses standard serdes without CDR, then it reduces circuit complexity, but it cannot properly handle USB 2.0 high-speed mode signals
Solution Approach 1:
The invention employs periodic sampling using four phase-shifted clock signals (0°, 90°, 180°, 270°) to capture data at optimal points in the signal cycle. This periodic action with multiple phases ensures that at least one sampling point will reliably capture the data value even in the presence of jitter or timing variations, thereby maintaining transmission reliability without requiring complex CDR circuits.
Solution Approach 2:
The system performs preliminary signal conditioning and sampling setup before actual data transmission begins. By pre-configuring the phase-shifted clock network and establishing the sampling framework in advance, the FPGA prepares the necessary infrastructure to reliably handle high-speed signals from the outset, ensuring transmission reliability is built into the system architecture rather than added as a corrective measure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables high-speed data communication between a host and an FPGA, effectively handling USB 2.0 high-speed mode without the need for a CDR circuit, thereby enhancing the connectivity and processing capabilities of FPGAs.
Implementation Method 1
a first differential comparator operable to identify a logic zero state at the P-channel and a second differential comparator operable to identify a logic zero state at the N-channel
Implementation Method 2
a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel
Implementation Method 3
a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift
Data Source
AI summary
A system containing a host and a device having a field-programmable gate array (“FPGA”) is disclosed. The system includes a set of configurable logic blocks (“LBs”), a bus, and a Universal Serial Bus (“USB”) interface. The configurable LBs, in one aspect, are able to be selectively programmed to perform one or more logic functions. The bus contains a P-channel and an N-channel operable to transmit signals in accordance with a high-speed USB protocol. The USB interface is configured to include a first differential comparator operable to identify a logic zero state at the P-channel and a second differential comparator operable to identify a logic zero state at the N-channel.