Fractal Analog Memory Array for High-Throughput Parallel Readout
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Solution Overview
Problem
Existing technologies face challenges in efficiently performing matrix-matrix multiplication operations required for tasks like speech recognition, image recognition, and computer graphics due to slow processes in reading resistive processing unit (RPU) values, which are crucial for deep neural network training.
Innovation Solution
A fractal analog random access memory device is designed with an array of sample and hold capacitors, readout transistors, and peripheral amplifiers, allowing for rapid and parallel access to large arrays of capacitors through fractal scaling and minimal voltage loss, enabling efficient matrix-matrix multiplication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional RPU read processes are used, then matrix-matrix multiplication can be performed, but read throughput is slow and power consumption is high
Solution Approach 1:
The memory array is divided into multiple subunits (R x C subunits) with each subunit having its own peripheral amplifier and ADC, enabling parallel read operations across multiple subunits simultaneously. This segmentation allows the read throughput to be increased by a factor of R when reading entire rows or C when reading entire columns, directly addressing the slow read throughput problem while distributing power consumption across multiple independent subunits.
Solution Approach 2:
The patent introduces a fractal hierarchical structure with multiple levels of subunits and shared amplifiers, creating a multi-dimensional readout architecture. This dimensional organization allows parallel reading across different levels and groups, significantly increasing throughput while the shared amplifier structure helps manage power consumption by reusing amplification resources across multiple subunits.
2Productivity
If array size is increased for better performance, then parallelism increases, but device complexity increases
Solution Approach 1:
The large memory array is segmented into R x C subunits with each subunit containing its own peripheral amplifier and ADC. This segmentation allows the system to achieve high parallelism and read throughput while keeping each individual subunit relatively simple and modular, making the overall complex system manageable through standardized repeating units.
Solution Approach 2:
The patent designs a universal readout structure where peripheral amplifiers and ADCs can serve multiple subunits through shared resources. The analog multiplexer and fractal hierarchical structure enable the same peripheral components to perform readout functions for multiple memory subunits, reducing overall device complexity while maintaining high parallelism and throughput capabilities.
3Speed
If sample and hold capacitors are used in array geometry, then rapid parallel access is enabled, but manufacturing precision requirements increase
Solution Approach 1:
The capacitor array is divided into R x C subunits with each subunit having its own sample and hold capacitors. This segmentation allows for standardized, modular fabrication of identical subunit blocks, reducing the overall manufacturing precision requirements compared to building a single large capacitor array. Each subunit can be manufactured using standard processes and then assembled into the complete array.
Solution Approach 2:
The patent employs sample and hold capacitors that can be selectively activated through control signals, allowing the system to change the effective capacitance configuration dynamically. This parameter change capability enables rapid parallel access by selectively connecting different capacitor groups while maintaining stable voltage levels during readout, achieving high speed without requiring extremely tight manufacturing tolerances on individual capacitor values.
Data Source
AI summary
A memory device that includes a plurality of memory cells including sample capacitors and hold capacitors in an array geometry; a readout transistor in electrical communication with the sample capacitors and hold capacitors; and a peripheral amplifier. The memory device further includes an analog multiplexer that controls digital and analog signal to the array of memory cells to provide for random access of the memory cells. The read transistor provides a single source follower transistor for each memory cell of the plurality of memory cells to the peripheral amplifier.