Fractional Frequency Divider With Dynamic Clock Masking Control
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Solution Overview
Problem
Conventional fractional frequency dividers have complex circuit designs and are limited to generating output clock signals with specific frequencies, making it difficult to achieve simpler and more flexible frequency division.
Innovation Solution
A fractional frequency divider comprising a plurality of registers, a counter, a control signal generator, and a clock gating circuit, which allows for the generation of output clock signals with various frequencies by masking or unmasking the input clock signal based on control signals generated from counter values and register settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional frequency divider uses multiple flip-flops connected in series, then the output clock frequency can be divided by 2^n, but the frequency resolution is limited and cannot achieve fractional frequencies
Solution Approach 1:
The frequency division function is segmented into multiple stages: a first frequency divider using flip-flops for integer division, and a second frequency divider using a counter and clock gating circuit for fractional division. This segmentation allows each stage to specialize in different aspects of frequency division, achieving both integer and fractional division capabilities while managing circuit complexity.
Solution Approach 2:
The patent introduces dynamic control mechanisms where the counter value and gate control signal can be adjusted to change the frequency division ratio dynamically. The clock gating circuit dynamically enables or disables clock signal passage based on counter state, allowing flexible fractional frequency division without redesigning the entire circuit.
2Adaptability or versatility
If a fractional frequency divider is designed to generate output clock signals with special frequencies, then frequency flexibility is improved, but the circuit design becomes complicated
Solution Approach 1:
The frequency divider circuit is designed with universal components that can perform multiple functions. The counter can operate in different modes, the clock gating circuit can handle both integer and fractional division, and the register can be configured for different division ratios. This multi-functionality allows the same circuit to achieve various frequency division ratios without requiring separate dedicated circuits for each function.
Solution Approach 2:
The patent introduces intermediate components such as the counter and gate control signal that mediate between the input clock and output clock. These intermediaries enable flexible frequency control by providing a mechanism to selectively pass or block clock cycles, achieving fractional frequency division without directly modifying the core flip-flop structure.
3Adaptability or versatility
If the frequency division ratio is changed dynamically, then adaptability is improved, but the circuit requires additional control mechanisms increasing complexity
Solution Approach 1:
The register is pre-configured with the desired frequency division ratio before operation. This preliminary setup allows the circuit to quickly switch between different division ratios by loading different values into the register, without requiring complex real-time calculation or adjustment mechanisms during operation.
Solution Approach 2:
The counter provides feedback to the gate control signal generation logic, enabling the circuit to track its current division state. This feedback mechanism allows the control logic to generate appropriate gate control signals that achieve the desired fractional frequency division while adapting to different operating conditions.
Data Source
AI summary
The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.