Digital Fractional Frequency Divider With Multi-Phase Retiming
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Solution Overview
Problem
Conventional frequency synthesizer circuit topologies for fractional frequency division suffer from slow startup times, high power consumption, and high jitter, often due to complexity.
Innovation Solution
The implementation of multi-phase clock generator circuitry, frequency divider circuitry, signal retiming circuitry, and signal combining circuitry, which generates multi-phase clock signals, performs digital frequency division, and combines retiming signals to produce an output clock with desired frequency and duty cycle, reducing complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional circuit topologies are used for fractional frequency division, then frequency division capability is achieved, but startup time increases and power consumption increases
Solution Approach 1:
The patent replaces conventional mixed-signal or analog circuit topologies with a completely digital implementation using flip-flops and logic circuits. This substitution of digital logic for analog/mixed-signal mechanisms enables faster startup times and reduced power consumption while maintaining fractional frequency division capability.
Solution Approach 2:
The frequency division function is segmented into multiple independent digital stages using flip-flops. Each flip-flop stage operates independently to divide the input frequency by a specific factor, allowing the system to achieve complex fractional division through composition of simple digital elements, thereby reducing overall power consumption and improving startup response.
2Device complexity
If conventional circuit topologies are used for fractional frequency division, then frequency division capability is achieved, but device complexity increases
Solution Approach 1:
The patent replaces complex analog phase-locked loop (PLL) mechanisms and analog frequency synthesis circuits with a purely digital architecture using flip-flops and logic gates. This substitution simplifies the circuit topology while improving jitter performance through the inherent stability of digital timing references.
Solution Approach 2:
The patent changes the operating parameters by using digital logic states and clocking mechanisms instead of analog voltage and current control. This parameter transformation from analog to digital domain reduces circuit complexity and improves reliability by eliminating analog noise and drift issues that cause jitter.
3Device complexity
If integer frequency division is used, then circuit complexity is reduced, but fractional frequency division capability is lost
Solution Approach 1:
The patent segments the frequency division function into multiple independent digital stages, where each stage can be configured for different division ratios. This segmentation allows the system to achieve integer division simplicity while combining stages to realize fractional division ratios, thus maintaining both low complexity and high flexibility.
Solution Approach 2:
The digital flip-flop based circuit serves multiple functions: it can perform integer frequency division when configured with simple feedback, and fractional frequency division when configured with additional logic control. This universal design eliminates the need for separate circuits for different division types, reducing overall complexity while enhancing adaptability.
Data Source
AI summary
Frequency synthesizer circuitry includes multi-phase clock generator circuitry, frequency divider circuitry, signal retiming circuitry, and signal combining circuitry. The multi-phase clock generator circuitry receives an input clock signal and generates a number of multi-phase clock signals. The frequency divider circuitry also receives the input clock signal and performs frequency division thereon to generate a reference signal. The signal retiming circuitry receives the reference signal and the multi-phase clock signals and generates a number of retiming signals. The signal combining circuitry combines two of the retiming signals to provide an output clock signal that has the same frequency as the reference signal but a different duty cycle.