Fractional Divider Circuit Using Phase Blending for Low Jitter
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Solution Overview
Problem
Conventional fractional dividers used in phase locked loops (PLLs) often introduce spurs and jitter when generating fractional frequencies, necessitating an improved solution for efficient frequency synthesis.
Innovation Solution
A fractional divider apparatus comprising a delay locked loop (DLL) with multiple taps, a phase blender, a state machine, a toggle circuit, a duty cycle correction circuit, and a sigma delta modulator, along with multiplexers and latches, which allows for independent optimization and reduced jitter by generating fractional clock signals with low deterministic jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional fractional dividers are used in PLLs to generate fractional frequencies, then frequency synthesis capability is improved, but spurs and jitter are introduced
Solution Approach 1:
The fractional divider is segmented into multiple independent components: integer divider, fractional divider, duty cycle correction circuit, and multiple output buffers. Each component processes specific portions of the division function, allowing optimization of each segment to minimize spurs and jitter while maintaining fractional frequency generation capability
Solution Approach 2:
A duty cycle correction circuit is introduced as an intermediary component between the fractional divider and the outputs. This mediator circuit corrects the duty cycle variations that cause spurs and jitter, thereby reducing harmful factors while preserving the fractional frequency synthesis function
2Measurement precision
If conventional fractional dividers are used, then fractional frequency generation is achieved, but deterministic jitter is increased
Solution Approach 1:
Different output buffers are provided with optimized duty cycles locally tailored to their specific functions. The duty cycle correction circuit provides localized correction to each fractional divider output, ensuring that each output path has optimal timing characteristics, thereby reducing deterministic jitter while maintaining high frequency resolution
Solution Approach 2:
The duty cycle parameter is dynamically adjusted and corrected through the duty cycle correction circuit. By changing the duty cycle parameter to optimal values, the circuit reduces deterministic jitter while preserving the precise frequency division capability
3Adaptability or versatility
If multiple outputs are provided from a single PLL, then versatility is improved, but phase matching and timing alignment become difficult
Solution Approach 1:
The PLL is segmented into independent fractional divider units, each with its own duty cycle correction circuit and output buffers. This segmentation allows each output to be independently optimized for phase and timing, making phase matching and timing alignment between multiple outputs straightforward while maintaining versatility
Solution Approach 2:
The duty cycle correction circuits operate with feedback mechanisms that monitor and adjust the timing and phase characteristics of each output. This feedback ensures automatic phase matching and timing alignment across multiple outputs, simplifying operation while enabling versatile multi-output functionality
Data Source
AI summary
A fractional divider has been provided that allows for division ratios of 1:1 to 1:2N-1 with fine fractional resolution. To accomplish this, a phase blender (which is under the control of a state machine) is used to “blend” or interpolate consecutive phases of a clock signal from a delay locked loop to achieve a low deterministic jitter, while a sigma delta modulator can also be used to maintain low deterministic jitter while achieving the desired frequency resolution.