Fractional Divider Error Correction for Low-Jitter PLL Clocks
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Solution Overview
Problem
Conventional fractional frequency dividers in clock generation circuits introduce jitter and quantization noise, requiring low bandwidth phase-locked loops and complex phase error correction, which are costly and inefficient, especially as clock signal frequencies increase.
Innovation Solution
A phase-locked loop with a digital phase/frequency detector and an input fractional divider that includes an analog divider, time-to-digital converter, and error correction circuit to generate jitter-free clock signals, allowing for wider bandwidth and reduced phase error correction needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional fractional frequency dividers are used to generate clock signals, then the circuit can operate at high frequencies, but jitter and quantization noise are introduced into the clock signals
Solution Approach 1:
The fractional frequency divider is segmented into multiple independent components: an integer frequency divider, a phase offset generator, and a multiplexer. The integer divider generates a base clock signal, the phase offset generator creates multiple phase-shifted versions, and the multiplexer selects the appropriate phase based on the fractional portion. This segmentation eliminates jitter and quantization noise by avoiding conventional fractional division techniques.
Solution Approach 2:
Multiple phase-shifted clock signals are generated in advance using the phase offset generator before the final selection is needed. By pre-generating all possible phase versions and storing them, the system can quickly switch between phases without introducing jitter or quantization noise during the frequency division process.
2Speed
If conventional fractional frequency dividers are used, then high speed clock signals can be generated, but complex phase error correction techniques are required
Solution Approach 1:
The phase error correction function is extracted from the main frequency division path and implemented separately through the phase offset generator. By taking out the phase adjustment functionality and making it independent, the system eliminates the need for complex feedback-based phase error correction circuits, reducing overall device complexity while maintaining high-speed operation.
Solution Approach 2:
Phase offsets are calculated and stored in advance in a lookup table within the phase offset generator, based on the fractional division ratio. This preliminary calculation eliminates the need for real-time phase error correction during operation, significantly reducing circuit complexity and enabling high-speed clock generation without complex correction techniques.
3Speed
If conventional fractional frequency dividers are used, then clock signals can be frequency-divided, but quantization noise is introduced requiring low bandwidth phase-locked loops
Solution Approach 1:
The frequency division operation is segmented into integer division and phase offset selection. The integer frequency divider performs the main division without quantization noise, while the fractional portion is handled by selecting from pre-generated phase-shifted signals. This segmentation eliminates quantization noise, allowing the phase-locked loop to operate with wider bandwidth without requiring complex noise filtering.
4Adaptability or versatility
If conventional fractional frequency dividers are used, then frequency division can be achieved, but the phase frequency detector must support large full-scale phase range
Solution Approach 1:
All possible phase positions are generated in advance by the phase offset generator and stored for immediate selection. By preparing all phase options beforehand, the phase frequency detector only needs to select from a fixed set of known phases rather than tracking large phase ranges, significantly reducing its complexity while maintaining full frequency division capability.
Data Source
AI summary
A clock product includes a phase-locked loop configured to generate an output clock signal based on an input digital value and a feedback digital value. The input digital value corresponds to a first clock edge of a frequency-divided input clock signal and the feedback digital value corresponds to a second clock edge of a feedback clock signal. The clock product includes an input fractional divider configured to generate the input digital value based on an input clock signal, a divider value, and an input clock period digital code corresponding to a period of the input clock signal.