Programmable Fractional Divider for Cycle-by-Cycle VCO Tuning
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Solution Overview
Problem
Existing locked loop circuits require more precise control over the divider's divisor value to generate selectable and precise VCO output signals, necessitating further development in programmable dividers for fine precision in clock signal generation.
Innovation Solution
A programmable-on-the-fly fractional divider circuit that includes a subtract-by-two and subtract-by-one circuit, multiplexers, and an asynchronous one-shot N+2 divider, allowing for dynamic adjustment of the divisor value on a cycle-by-cycle basis, enabling precise division of clock signals by fractional values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a programmable divider is used to enable selectable VCO output frequencies, then the adaptability of the system is improved, but the device complexity increases
Solution Approach 1:
The divider circuit implements dynamic divisor value adjustment on a cycle-by-cycle basis, allowing the division ratio to change dynamically without requiring complex reconfiguration. The divisor can be updated each clock cycle through the use of flip-flops and multiplexers that capture and apply new divisor values synchronously with the clock signal, enabling flexible frequency selection while maintaining manageable circuit complexity.
Solution Approach 2:
The divider circuit is segmented into multiple functional blocks including subtract-by-two circuitry, subtract-by-one circuitry, multiplexers, and flip-flops. Each block performs a specific function in the division process, allowing the overall complex function of fractional division to be achieved through composition of simpler, well-defined sub-functions. This modular segmentation makes the complex operation of fractional division more manageable and implementable.
2Measurement precision
If fine precision division is implemented to generate very precise VCO output signals, then the measurement precision is improved, but the device complexity increases
Solution Approach 1:
The circuit achieves fine precision division by dynamically changing the divisor parameter on a cycle-by-cycle basis. By allowing the divisor to vary between cycles and to take fractional values through the combination of integer division and fractional adjustment circuits, the system achieves high precision frequency control without requiring excessively complex circuitry. The precision is achieved through parameter variation rather than through increased circuit complexity alone.
Solution Approach 2:
The circuit performs preliminary subtraction operations (subtract-by-two and subtract-by-one) before the final division to prepare the divisor value. These preliminary actions on the divisor allow the main division operation to achieve higher precision by working with pre-adjusted values, reducing the complexity of the main division circuit while maintaining fine precision control over the output frequency.
3Productivity
If dynamic adjustment of divisor value is enabled on a cycle-by-cycle basis, then the productivity is improved, but the device complexity increases
Solution Approach 1:
The divider circuit is designed to automatically capture and apply new divisor values on each clock cycle without requiring external intervention or complex control logic. The flip-flops and multiplexers are configured to self-update the divisor value synchronously with the clock signal, enabling rapid frequency adjustment while keeping the control mechanism relatively simple. The circuit serves itself by automatically implementing the frequency change when new divisor values are provided.
Solution Approach 2:
The dynamic adjustment of the divisor value occurs periodically with each clock cycle, allowing the frequency to be adjusted at regular intervals. This periodic update mechanism enables fast frequency switching by simply changing the divisor value at the next clock edge, achieving high productivity without requiring complex continuous control mechanisms. The regular periodic nature of the updates simplifies the timing and control logic.
Data Source
AI summary
A divider circuit includes a subtract-by-two circuit receiving MSBs of an input and producing a subtracted-by-two output, a subtract-by-one circuit receiving the MSBs and producing a subtracted-by-one output, a first multiplexer passing the subtracted-by-two or the subtracted-by-one output based on a first control signal, a second multiplexer passing output of the first multiplexer or the MSBs based on a second control signal to produce an asynchronous divisor. An asynchronous one-shot N+2 divider divides an input clock by the asynchronous divisor to produce a first divided signal. An output flip-flop receives the first divided signal and is clocked by an inverse of the input clock to produce a second divided signal. A third multiplexer passes the first divided signal or the second divided signal in response to a select load signal to produce a multiplexer output. A divider divides the multiplexer output by a set divisor to produce an output clock.