Fractional Frequency Divider Circuit for High-Purity Frequency Synthesis
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Solution Overview
Problem
Existing frequency synthesis technologies face challenges in generating specific carrier frequencies with high-resolution fractional ratios, particularly in low-power wireless communication systems like Bluetooth Low Energy (BLE) and Internet of Things (IoT) devices, requiring improved spectral purity and energy efficiency.
Innovation Solution
A frequency dividing circuit that utilizes a controlled oscillator and a frequency dividing circuit to generate a frequency dividing circuit output signal with a decimal ratio, using positive and negative binary words to achieve a fractional frequency division, combined with a phase locked loop for precise frequency locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional frequency synthesis methods are used, then frequency generation is achieved, but spectral purity and resolution are insufficient for high-precision applications
Solution Approach 1:
The frequency division ratio is segmented into integer and fractional parts, with the fractional part further divided into multiple bits (e.g., 6-bit fractional division). This segmentation allows independent optimization of integer division (affecting spectral purity) and fractional division (affecting frequency resolution), resolving the contradiction between the two requirements.
Solution Approach 2:
The frequency synthesizer dynamically adjusts the division ratio by combining integer and fractional components, allowing the system to adaptively optimize both spectral purity and frequency resolution based on application requirements. The dynamic control of division ratios enables high-precision frequency synthesis while maintaining good spectral characteristics.
2Measurement precision
If high-resolution fractional frequency division is implemented, then frequency precision is improved, but circuit complexity increases
Solution Approach 1:
The complex frequency division function is segmented into multiple manageable modules: integer division unit, fractional division unit with multiple bits, and control logic. This modular segmentation reduces overall circuit complexity by allowing each module to be independently designed and optimized, while collectively achieving high-resolution frequency division.
Solution Approach 2:
The frequency division ratio is extended from one-dimensional integer division to two-dimensional division by adding fractional bits. This dimensional extension enables high-resolution frequency control without proportionally increasing circuit complexity, as the fractional part uses efficient bit-based control rather than full parallel implementation.
3Measurement precision
If fractional frequency division with decimal ratios is achieved, then frequency synthesis precision is improved, but power consumption increases
Solution Approach 1:
The frequency synthesis function is segmented into integer and fractional components, allowing the system to use coarser integer division (lower power) combined with fine-resolution fractional division (higher precision but controlled power). This segmentation enables high precision while managing power consumption through hierarchical division strategies.
Solution Approach 2:
The system implements partial fractional division by using a limited number of fractional bits (e.g., 6-bit fractional division) rather than full-precision division. This partial implementation achieves sufficient frequency synthesis precision for most applications while significantly reducing the computational complexity and power consumption associated with full-precision fractional division.
Data Source
AI summary
In various embodiments, a frequency dividing circuit is provided. The frequency dividing circuit may include a first circuit including an m-bit multiplexer configured to receive a positive binary word and a negative binary word as inputs. The frequency dividing circuit may receive a controlled oscillator output signal and a complement of the controlled oscillator output signal, generate a frequency dividing circuit output signal from the controlled oscillator output signal and the complement of the controlled oscillator output signal using the positive binary word and the negative binary word. A ratio of the frequency dividing circuit output signal frequency to the controlled oscillator output signal frequency is a decimal value greater than zero and less than one and is determined using a ratio of a value of the positive binary word to a sum of the value of the positive binary word and an absolute value of the negative binary word.