Fractional-N Synthesizer Reference Clock Chain for Lower Phase Noise
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Solution Overview
Problem
Frequency synthesizers face degradation in phase noise performance, especially when generating high-frequency signals, due to noise associated with the sigma-delta modulator, which limits their effectiveness and flexibility in optimizing loop bandwidth.
Innovation Solution
A cascaded system comprising a frequency doubler and a frequency multiplier is used to increase the frequency of the reference clock signal, providing a low-noise, high-frequency clock signal suitable for fractional-N frequency synthesizers, thereby minimizing phase noise contributions and allowing for wider loop bandwidth optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a fractional-N frequency synthesizer uses a sigma-delta modulator to generate high-frequency output signals, then the output frequency range is extended, but phase noise performance deteriorates due to quantization noise
Solution Approach 1:
The patent divides the frequency multiplication process into two separate stages: an integer frequency multiplier (first frequency multiplier) and a fractional-N frequency synthesizer (second frequency multiplier). The integer multiplier handles the coarse frequency multiplication with high precision, while the fractional synthesizer handles the fine frequency adjustment. This segmentation prevents the sigma-delta modulator from operating at extremely high multiplication ratios, thereby reducing quantization noise and improving phase noise performance.
Solution Approach 2:
The patent introduces an integer frequency multiplier as an intermediary stage between the reference clock and the fractional-N frequency synthesizer. This intermediary handles the bulk of the frequency multiplication task, allowing the fractional synthesizer to operate with a reduced multiplication ratio. The intermediary effectively filters out the quantization noise that would otherwise be generated by a high-ratio fractional synthesizer operating directly from the reference clock.
2Speed
If the sigma-delta modulator operates at high multiplication ratios, then higher output frequencies are achieved, but quantization noise increases and degrades synthesizer performance
Solution Approach 1:
The patent segments the frequency multiplication function into two distinct blocks: an integer frequency multiplier that performs coarse multiplication, and a fractional-N frequency synthesizer that performs fine multiplication. This segmentation reduces the multiplication ratio required from the sigma-delta modulator, thereby reducing quantization noise while still achieving the desired high output frequency.
3Device complexity
If a single frequency multiplier is used to achieve high frequency output, then device complexity is reduced, but phase noise performance deteriorates
Solution Approach 1:
The patent divides the frequency multiplication function into two separate frequency multiplier blocks: an integer frequency multiplier and a fractional-N frequency synthesizer. This segmentation improves phase noise performance by preventing the sigma-delta modulator from operating at extremely high multiplication ratios, while the added complexity of the second frequency multiplier block is justified by the significant improvement in output signal quality.
Data Source
AI summary
A frequency synthesizing system includes a clock generator to generate a reference clock signal, a frequency doubler to generate a frequency-doubled clock signal in response to rising edges and falling edges of the reference clock signal, a frequency multiplier to generate a frequency-multiplied clock signal in response to either rising edges or falling edges of the frequency-doubled clock signal, and a fractional-N synthesizer coupled to the frequency multiplier to generate an output clock signal in response to the frequency-multiplied clock signal.