Fractional-N PLL Clock Recovery for Low-Jitter Wireline Links
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Solution Overview
Problem
Conventional clock and data recovery (CDR) devices are inadequate for high data rate applications due to difficulties in achieving low jitter performance, susceptibility to electromagnetic coupling, and stability issues, particularly in designs using phase interpolators and ring oscillators.
Innovation Solution
The implementation of a fractional-N phase-lock loop (PLL) architecture in CDR devices, which includes a phase detector, loop filter, and a fractional-N PLL with components like charge pumps and sigma delta modulators, provides low jitter performance, immunity to noise, and stability, eliminating the need for phase interpolators and reducing electromagnetic coupling susceptibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional CDR devices use phase interpolators and ring oscillators, then device complexity is reduced, but jitter performance deteriorates and electromagnetic coupling susceptibility increases
Solution Approach 1:
The patent changes the fundamental parameters of the oscillator design by replacing ring oscillators with delay-locked loop-based oscillators and phase interpolators with configurable delay elements. This parameter change enables precise phase control while reducing jitter and electromagnetic coupling, resolving the contradiction between device complexity and reliability.
2Ease of manufacture
If conventional CDR devices use phase interpolators, then ease of manufacture is improved, but noise immunity deteriorates
Solution Approach 1:
The patent substitutes the mechanical/electrical phase interpolator system with a digital-based delay control system. By using digitally controlled delay elements and programmable logic, the system achieves better noise immunity while remaining manufacturable through standard digital integration processes.
3Reliability
If fractional-N PLL architecture is implemented, then jitter performance is improved, but device complexity increases
Solution Approach 1:
The patent implements a fractional-N PLL architecture where a single integrated circuit performs multiple functions: phase detection, fractional division, delay control, and oscillation. This multi-functional design achieves low jitter performance while managing device complexity through functional integration rather than separate components.
4Object-affected harmful factors
If fractional-N PLL architecture is implemented, then noise immunity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates calibration circuits and control logic that automatically adjust delay element characteristics during operation. This self-calibration capability compensates for manufacturing variations, achieving high noise immunity without requiring extremely tight manufacturing precision for the delay elements.
Data Source
AI summary
The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.