Multi-Phase Fractional PLL Divider for Low-Jitter Clock Feedback
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing fractional PLLs experience significant jitter due to variations in output signal edges, particularly in alternating division fractional PLLs, which affect the precision and alignment of clock edges.
Innovation Solution
A fractional frequency synthesizer utilizing a multi-phase clock vector and multi-phase divider circuitry to select a clock signal based on a rollover value, minimizing jitter by using a voltage-controlled ring oscillator to generate phase-offset clock signals and an accumulator to determine the optimal clock signal for generating a fractional frequency signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If alternating division fractional PLL is used to generate fractional frequency signals, then frequency resolution is improved, but jitter increases significantly
Solution Approach 1:
The clock signal is divided into multiple phases (e.g., 4 phases) using a multi-phase clock generator. Each phase is offset by a specific angle (e.g., 90 degrees), allowing the system to select different phases based on the accumulator rollover value to minimize jitter in the feedback signal.
Solution Approach 2:
The system dynamically selects which clock phase to use for the feedback signal based on the accumulator rollover value. This dynamic selection allows the system to adapt to different frequency division requirements while maintaining minimal jitter, resolving the contradiction between frequency resolution and signal stability.
2Reliability
If multi-phase clock generator with voltage-controlled ring oscillator is used, then jitter is reduced, but device complexity increases
Solution Approach 1:
The multi-phase clock generator serves multiple functions: it generates the reference clock signal, creates multiple phase-offset versions of the clock, and provides the basis for dynamic phase selection. This multi-functionality reduces the need for separate jitter-reduction circuits, thereby limiting the increase in overall device complexity.
Solution Approach 2:
The phase selection logic acts as an intermediary between the multi-phase clock generator and the feedback path. It selectively routes the appropriate clock phase based on the accumulator rollover value, implementing jitter reduction without requiring complex circuit modifications throughout the entire PLL system.
3Measurement precision
If dynamic clock phase selection is implemented, then clock edge alignment is improved, but manufacturing precision requirements increase
Solution Approach 1:
The system uses periodic accumulator rollover events to trigger phase selections in a systematic manner. By tying phase selection to the regular periodic rollover of the accumulator counter, the system achieves consistent clock edge alignment without requiring extremely precise manual adjustment of phase offsets during manufacturing.
Solution Approach 2:
The accumulator rollover value provides feedback information about the current division state, which is used to select the appropriate clock phase. This feedback mechanism ensures that the selected phase consistently aligns with the required clock edge timing, reducing sensitivity to manufacturing variations in phase offset values.
Data Source
AI summary
A fractional frequency synthesizer, a fractional PLL, and a method for generating a fractional frequency signal based on a reference signal are provided. An example fractional frequency synthesizer includes a multi-phase clock generator configured to generate a clock vector comprising a plurality of clock signals, each oscillating according to a fractional frequency in relation to the reference frequency and each clock signal offset by a phase offset. The fractional frequency synthesizer includes multi-phase divider circuitry configured to select a clock signal from the clock vector to generate a fractional frequency feedback signal. An accumulator configured to increment a count and a rollover detector configured to determine a rollover value associated with a rollover event on the accumulator are further included. A clock signal is selected based on the rollover value and the fractional frequency feedback signal is generated based at least in part on the selected clock signal.