Fractional-N PLL Self-Biasing for PVT-Stable Loop Bandwidth
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Solution Overview
Problem
Variations in manufacturing process, voltage, or temperature (PVT) cause variations in loop parameters of phase-locked loops, degrading the timing and noise characteristics of clock signals in fractional-N frequency synthesizers.
Innovation Solution
A method and circuit design for fractional-N frequency synthesizers that generate a bias signal based on the control voltage and frequency divider value, using a selectable loop filter resistance and capacitance replica of a ring oscillator load, to achieve loop parameter independence from PVT variations, and implement techniques to counteract timing and magnitude mismatches in current pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional phase-locked loop circuits are used, then the basic frequency synthesis function is achieved, but the loop parameters vary with PVT variations degrading timing and noise characteristics
Solution Approach 1:
The patent dynamically adjusts loop filter resistance and charge pump current based on detected PVT conditions to maintain optimal loop parameters. Specifically, the loop filter resistance is adjusted according to process and temperature variations, and the charge pump current is scaled based on frequency divider value to compensate for PVT effects on loop bandwidth and damping factor
Solution Approach 2:
The patent implements feedback mechanisms where the actual loop parameters are monitored and used to adjust the bias signals and filter components. The control voltage from the VCO and frequency divider value are fed back to the bias signal generator to dynamically adjust the charge pump current and maintain stable loop characteristics despite PVT variations
2Measurement precision
If fractional-N frequency synthesis is implemented, then frequency resolution is improved, but quantization noise and fractional spurs increase
Solution Approach 1:
The patent employs dynamic adjustment of the charge pump current based on the frequency divider value to optimize the trade-off between frequency resolution and noise performance. By dynamically scaling the charge pump current according to the division ratio, the system maintains low quantization noise while achieving fine frequency resolution through fractional-N synthesis
Solution Approach 2:
The patent changes the charge pump current parameter dynamically based on the frequency divider value to reduce quantization noise. The bias signal generator adjusts the charge pump current proportionally to the division ratio, optimizing the signal-to-noise ratio while maintaining the frequency synthesis function
3Manufacturing precision
If loop bandwidth is increased to reduce noise, then timing characteristics improve, but PVT variations have greater impact on loop parameter stability
Solution Approach 1:
The patent implements adaptive parameter adjustment where the loop filter resistance and charge pump current are dynamically changed based on PVT conditions. This allows the loop bandwidth to be optimized for timing characteristics while simultaneously compensating for PVT variations through feedback-adjusted parameters
Solution Approach 2:
The patent uses feedback from the VCO control voltage and frequency divider to continuously adjust the loop parameters. This feedback mechanism ensures that the loop bandwidth maintains its noise-reduction benefits while remaining stable against PVT variations through real-time parameter optimization
Data Source
AI summary
A technique for reducing effects of variations in process, voltage, and temperature (PVT) on the performance of a fractional-N frequency synthesizer includes making loop parameters, e.g., damping factor ζ and loop bandwidth ωN, first-order independent of PVT variations. In an embodiment of a fractional-N frequency synthesizer, a voltage-controlled oscillator is implemented using a ring-oscillator realized by an odd number of inverter stages. By making the loop parameters a multiple of frequency fREF and a ratio of components (e.g., C1/Cst, where capacitance Cst represents the load of each stage of the ring oscillator) and self-biasing the phase-locked loop, the technique makes the ratio of loop bandwidth ωn to the operating frequency fCLKOUT constant in response to PVT variations.