Sliced Charge Pump Control in Fractional-N PLLs for Low Phase Noise
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Solution Overview
Problem
Fractional-N phase-locked loops (PLLs) face challenges in reducing phase noise without increasing power consumption and circuit area, as existing methods require complex calibration mechanisms to avoid noise folding issues.
Innovation Solution
A fractional-N PLL architecture with sliced charge pump control, utilizing multiple current sources and phase frequency detectors, and a divided clock controller to manage variable delays, reducing phase noise through sigma-delta modulation without requiring additional calibration mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a frequency divider with varying divisor is used to synthesize non-integer frequencies, then frequency synthesis capability is improved, but phase noise increases
Solution Approach 1:
The charge pump is divided into multiple parallel charge pumps, each with its own current source and phase frequency detector. This segmentation allows the system to achieve fractional-N synthesis while reducing phase noise by distributing the modulation across multiple independent paths, preventing noise folding issues that occur in single-path implementations.
2Object-generated harmful factors
If calibration mechanisms are added to reduce phase noise, then phase noise performance is improved, but circuit area and power consumption increase
Solution Approach 1:
The sliced charge pump architecture inherently prevents noise folding issues through its parallel structure and integer-multiple delay relationships. The system self-corrects timing mismatches by design, eliminating the need for external calibration mechanisms or pseudo-random permutation scrambling circuits, thus reducing circuit area and power consumption while maintaining low phase noise.
3Object-generated harmful factors
If calibration mechanisms are added to reduce phase noise, then phase noise performance is improved, but power consumption increases
Solution Approach 1:
The parallel sliced charge pump structure with integer-multiple delay relationships inherently avoids noise folding, allowing the system to achieve low phase noise without requiring power-hungry calibration circuits or pseudo-random permutation scrambling mechanisms. The architecture self-manages timing alignment through its structural design.
4Object-generated harmful factors
If multiple current sources are used to reduce phase noise, then phase noise performance is improved, but device complexity increases
Solution Approach 1:
The charge pump is segmented into multiple parallel paths with integer-multiple delay relationships. This segmentation reduces phase noise by distributing the modulation function across independent current sources while maintaining a regular, systematic structure that is easier to implement and control than alternative approaches.
Solution Approach 2:
Each slice of the charge pump performs multiple functions: it generates the required charge current, provides timing reference through its delay relationship with other slices, and contributes to noise reduction through parallel operation. This multi-functionality reduces the need for separate dedicated circuits.
Data Source
AI summary
A fractional-N phase locked loop (PLL) and a sliced charge pump (CP) control method thereof are provided. The fractional-N PLL includes a first current source, a first phase frequency detector (PFD), a second current source, a second PFD, and a divided clock controller. The first current source provides a first current. The first PFD generates a first detection signal according to a first divided clock, for controlling the first current source, wherein the first divided clock is generated according to an oscillation clock having an oscillation period. The second current source provides a second current. The second PFD generates a second detection signal according to a second divided clock, for controlling the second current source. The divided clock controller controls the second divided clock based on a variable delay relative to the first divided clock, wherein the variable delay is an integer times the oscillation period.