F-RAM Fabrication via Ferroelectric Capacitor Integration
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Solution Overview
Problem
Conventional methods for fabricating ferroelectric random-access memories (F-RAM) require additional mask and processing steps, increasing fabrication time, costs, and defect density due to the separate fabrication of ferroelectric capacitors and CMOS transistors, which deviates from the standard CMOS process flow.
Innovation Solution
The integration of ferroelectric capacitors directly into the CMOS process flow using a method that forms a ferroelectric capacitor with a bottom electrode electrically coupled to a MOS transistor diffusion region through a contact, minimizing changes to the CMOS process flow and utilizing a dual-damascene process to lower the total height of the ferro stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ferroelectric capacitors are fabricated in a separate layer overlying or isolated from the MOS transistor layer, then the ferroelectric capacitor can be formed with appropriate materials and processes, but the fabrication time, costs, and defect density increase due to several extra mask and processing steps
Solution Approach 1:
The patent merges the fabrication of ferroelectric capacitors and CMOS transistors into a single integrated process. The ferroelectric capacitor is formed within the same layer as the MOS transistor, eliminating the need for separate fabrication layers and isolation steps. This integration reduces the total number of mask and processing steps while maintaining the functionality of both components.
Solution Approach 2:
The patent employs a universal CMOS-compatible process that can fabricate both ferroelectric capacitors and MOS transistors using the same materials and processing steps. The ferroelectric capacitor utilizes the same inter-layer dielectric and contact structures as the transistor, allowing a single process flow to serve multiple functions and eliminate redundant steps.
2Ease of manufacture
If conventional separate fabrication methods are used for ferroelectric capacitors and CMOS transistors, then each component can be optimized independently, but the fabrication cost and defect density increase
Solution Approach 1:
The patent combines the fabrication processes for ferroelectric capacitors and CMOS transistors into a single integrated flow. By forming both components in the same layer using the same mask and processing steps, the patent eliminates redundant operations that increase cost and introduce defects, while maintaining the ability to optimize each component's performance.
3Adaptability or versatility
If ferroelectric capacitors are formed with standard CMOS processes, then process compatibility is achieved, but the materials and processes typically used to fabricate ferroelectric capacitors differ significantly from baseline CMOS process flow and can detrimentally impact MOS transistors
Solution Approach 1:
The patent applies local quality by using CMOS-compatible materials and processes for the ferroelectric capacitor while maintaining distinct functional regions. The ferroelectric capacitor is formed with appropriate dielectric properties in its specific location, using the same inter-layer dielectric and contact structures as the transistor, ensuring both components have their required properties without compromising the other.
Data Source
AI summary
Non-volatile memory cells including complimentary metal-oxide-semiconductor transistors and embedded ferroelectric capacitor and methods of forming the same are described. In one embodiment, the method includes forming on a surface of a substrate a gate level including a gate stack of a MOS transistor, a first dielectric layer overlying the MOS transistor and a first contact extending through the first dielectric layer from a top surface thereof to a diffusion region of the MOS transistor. A local interconnect (LI) layer is deposited over the top surface of the first dielectric layer and the first contact, a ferro stack including a bottom electrode, a top electrode and ferroelectric layer there between deposited over the LI layer, and the ferro stack and the LI layer patterned to form a ferroelectric capacitor and a LI through which the bottom electrode is electrically coupled to the diffusion region of the MOS transistor.