FRAM Layout Compiler Using Segmented Array Design
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Solution Overview
Problem
Ferroelectric random access memory (FRAM) designs have been labor-intensive and time-consuming due to the lack of compilers, unlike static and dynamic random access memory (SRAM and DRAM), which can automate layout generation, leading to a need for a compiler that can efficiently design FRAM layouts.
Innovation Solution
A compiler system for generating a layout for FRAM, comprising array segments with ferroelectric memory cells, sensing circuits, plate drivers, row interface circuits, error correcting code logic, and a controller, along with computer code for receiving specifications and assembling the layout based on design rules, enabling efficient FRAM design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FRAM is designed using custom design methods, then design flexibility and customization are improved, but design time and labor intensity increase significantly
Solution Approach 1:
The FRAM array is divided into multiple array segments, each with its own set of bitline cells, plateline cells, and sense amplifiers. This segmentation allows the compiler to generate standardized modular units that can be assembled automatically, reducing design time while maintaining flexibility through configurable segment arrangements.
Solution Approach 2:
The compiler accepts various design parameters (array size, segment configuration, cell arrangement) and automatically generates layouts based on these parameters. This parameter-driven approach enables design flexibility without requiring custom manual design for each configuration, significantly reducing design time.
2Area of stationary object
If FRAM array segments are arranged with shared sensing circuits, then circuit integration and area efficiency are improved, but design complexity increases
Solution Approach 1:
Sensing circuits are designed to serve multiple array segments simultaneously. Each sense amplifier can handle bitlines from different segments, allowing shared resources that reduce overall area while the compiler automatically manages the complexity of interconnections through systematic layout generation.
Solution Approach 2:
The compiler acts as an intermediary that automatically generates the complex interconnection layout between array segments and shared sensing circuits. This automation transforms the complex design task into a parameter specification task, reducing design complexity while achieving area-efficient layouts.
3Manufacturing precision
If bitline cells and plateline cells are systematically arranged with associated wordlines, then manufacturing consistency and design standardization are improved, but layout complexity increases
Solution Approach 1:
The compiler pre-establishes systematic arrangement rules for bitline cells, plateline cells, and wordlines before generating the actual layout. This preliminary structuring ensures manufacturing consistency through standardized patterns while the automation handles the complexity of arranging these elements according to the predefined rules.
Data Source
AI summary
A computer program for generating a layout for a ferroelectric random access memory (FRAM) that is embodied on a non-transitory storage medium and executable by a processor is provided. FRAM specifications are received, and an FRAM floorplan and design rules are retrieved from the non-transitory storage medium. The layout for the FRAM based on the FRAM specifications and design rules is then assembled.