Nonvolatile Logic Array with FRAM State Retention
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Solution Overview
Problem
Existing portable electronic devices face challenges in reducing leakage current during standby power mode, requiring continuous power to retain state information, which is inefficient for battery-operated devices and energy harvesting applications.
Innovation Solution
The implementation of non-volatile logic (NVL) using ferroelectric random access memory (FRAM) allows for complete power removal without losing state information, enabling instant-on capabilities and reducing energy consumption by using NVL arrays to store and restore flip-flop states within a System on Chip (SoC).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shadow latch is used to retain state information during standby power mode, then data retention is achieved, but leakage current is reduced only partially and continuous power is still required
Solution Approach 1:
The patent changes the fundamental parameter of state retention from volatile (shadow latch requiring continuous power) to non-volatile (FRAM). By using ferroelectric random access memory with hysteresis characteristics, the circuit maintains state information without continuous power supply, achieving complete elimination of leakage current during standby while preserving data retention capability
Solution Approach 2:
The patent replaces the mechanical/electrical shadow latch mechanism with a ferroelectric memory mechanism. Instead of using transistor-based latches that require continuous power to maintain state, the invention uses ferroelectric material properties (hysteresis loop) to store state information, substituting the entire power-dependent retention mechanism with a power-independent ferroelectric storage mechanism
2Productivity
If continuous power is provided to logic circuits, then system performance is maintained, but energy consumption increases
Solution Approach 1:
The patent implements dynamic power management where the logic circuit power state changes based on operational requirements. During active mode, full power is provided for optimal performance. During standby mode, power is completely removed from the logic circuit while state is preserved in FRAM. This dynamic switching between powered and unpowered states enables zero-leakage standby without compromising active performance
Solution Approach 2:
The patent performs preliminary action by storing the state of logic circuits in FRAM before power removal. The snapshot capture mechanism saves the logical state to non-volatile memory in advance, allowing the logic circuit to be completely powered down without losing operational state. This preliminary state preservation enables complete power removal while maintaining the ability to restore full performance
3Loss of energy
If power is completely removed from logic circuit, then energy consumption is minimized, but state information is lost
Solution Approach 1:
The patent introduces FRAM as an intermediary between the logic circuit and power supply. The ferroelectric memory acts as a buffer that receives and preserves state information from the logic circuit before power removal. This intermediary storage mechanism decouples the logic circuit from continuous power requirements, enabling complete power removal while preventing state information loss through the intermediary FRAM storage
4Loss of energy
If snapshot capture is implemented to save logic state, then power removal is enabled, but additional circuitry and complexity are required
Solution Approach 1:
The patent merges the snapshot capture functionality with the existing FRAM memory structure. Instead of adding separate complex retention circuits, the design integrates the state capture mechanism directly into the FRAM interface. The same FRAM array and control logic that provide non-volatile storage also serve the snapshot capture function, combining multiple functions into a unified structure that reduces overall circuit complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables zero-leakage power mode and rapid system restoration, optimizing energy usage and extending battery life in portable devices, particularly suitable for energy harvesting applications where power is intermittent.
Implementation Method 1
a first ferroelectric capacitor (FeCap) of a first bit cell in the array of bit cells coupled to the D input of the modified flip-flop
Data Source
AI summary
A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines. An AND gate is coupled to the m bit lines and has an output line coupled to an input of a test controller on the SoC. An OR gate is coupled to the m bit lines and has an output line coupled to an input of the test controller.