F-RAM Cell Fabrication via Pre-Patterned Barrier Structure
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Solution Overview
Problem
The existing methods for fabricating ferroelectric random access memories (F-RAM) with embedded ferroelectric capacitors and CMOS transistors are costly, increase defect density, and require complex processing steps, leading to larger cell sizes and lower yields due to incompatibility of materials and processes.
Innovation Solution
A method that forms a barrier structure over contacts in the CMOS layer, including an oxygen barrier layer and a bottom electrode, followed by a hydrogen barrier layer, to integrate ferroelectric capacitors with minimal changes to the standard CMOS process flow, reducing the number of masks and processing steps, and using a ferroelectric stack with a thin bottom electrode transition layer to form a ferroelectric capacitor with improved aspect ratio and reduced size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing methods for fabricating F-RAM with embedded ferroelectric capacitors are used, then ferroelectric memory functionality is achieved, but fabrication cost increases and defect density increases
Solution Approach 1:
The patent merges the ferroelectric capacitor fabrication process with the standard CMOS process flow by forming the bottom electrode, oxygen barrier layer, and hydrogen barrier layer using the same deposition and patterning equipment and steps already present in the CMOS manufacturing line. This integration eliminates the need for separate, specialized ferroelectric processing equipment and reduces overall fabrication cost while maintaining low defect density through process compatibility.
Solution Approach 2:
The patent creates a multi-functional barrier structure that serves multiple purposes: the oxygen barrier layer prevents oxygen diffusion to protect the ferroelectric layer, the hydrogen barrier layer prevents hydrogen diffusion to maintain CMOS transistor integrity, and the bottom electrode layer provides electrical connection. This universal structure handles multiple protection and functional requirements within a single integrated fabrication sequence, reducing both cost and complexity.
2Adaptability or versatility
If complex processing steps are used to integrate ferroelectric capacitors with CMOS transistors, then ferroelectric memory functionality is achieved, but the number of masks and processing steps increases
Solution Approach 1:
The patent performs preliminary actions by forming the bottom electrode layer, oxygen barrier layer, and hydrogen barrier layer during the standard CMOS fabrication process before the ferroelectric layer is deposited. The bottom electrode pattern is pre-formed with appropriate spacing and positioning, and the barrier layers are pre-deposited and pre-patterned to prevent contamination during subsequent ferroelectric processing. This preliminary preparation enables seamless integration without requiring additional complex processing steps later.
Solution Approach 2:
The patent introduces barrier layers as intermediary structures between the CMOS transistor region and the ferroelectric capacitor region. The oxygen barrier layer acts as an intermediary to prevent oxygen from reaching the ferroelectric layer, while the hydrogen barrier layer serves as an intermediary to prevent hydrogen from reaching the CMOS transistor. These intermediary layers facilitate integration by mediating the interface between incompatible materials and processes.
3Productivity
If standard integration methods are used, then ferroelectric capacitors are formed, but cell size increases and yields decrease
Solution Approach 1:
The patent applies local quality by forming the bottom electrode, oxygen barrier layer, and hydrogen barrier layer only in specific local regions where ferroelectric capacitors need to be formed, rather than across the entire CMOS substrate. The barrier structure is selectively patterned over contact regions, and the ferroelectric layer is deposited only where needed. This localized approach minimizes the area occupied by ferroelectric structures and reduces cell size while maintaining high yield through precise spatial control.
Solution Approach 2:
The patent transitions from planar integration to vertical integration by stacking the bottom electrode layer, oxygen barrier layer, and hydrogen barrier layer in multiple dimensions above the CMOS transistor. This vertical stacking allows the ferroelectric capacitor to be formed in the third dimension (height) rather than requiring additional lateral space, thereby reducing the overall cell footprint and increasing productivity without compromising yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes changes to the CMOS process flow, reduces defect density, lowers fabrication costs, and enables tighter design rules, resulting in smaller F-RAM cell sizes and higher yields by reducing the aspect ratio of ferroelectric capacitors and eliminating the need for deep vias, while maintaining the integrity of CMOS transistors.
Implementation Method 1
depositing a bottom electrode layer over an oxygen barrier layer
Implementation Method 2
encapsulating the patterned bottom electrode and barrier layers with a hydrogen (H2) barrier layer
Implementation Method 3
After the electric field is removed, the dipoles retain their polarization state. Data is stored in the cells as one of two possible electric polarization states
Data Source
AI summary
Structure and method of fabrication of F-RAM cells are described. The F-RAM cell include ferroelectric capacitors forming over and with a pre-patterned barrier structure which has a planarized/chemically and/or mechanically polished top surface. The pre-patterned barrier structure includes multiple oxygen barriers having a structure of a bottom electrode layer over an oxygen barrier layer. The bottom electrode layer forms at least a part of the bottom electrode of the ferroelectric capacitor formed thereon.