Frequency Divider Asymmetric Latch Design for RF Transceivers
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Solution Overview
Problem
Existing frequency dividers in RF communication systems suffer from noise issues, power consumption problems, and phase mismatch errors, leading to inefficient and costly designs, especially at high frequencies.
Innovation Solution
A frequency divider design utilizing stronger latches for I and Q channels, where larger devices are used for master latches and smaller devices for slave latches, to reduce power consumption and phase noise, while maintaining accurate operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a divide by four frequency divider is used to reduce noise and interference, then receiver performance is improved, but power consumption increases due to requiring high frequency VCO with buffers capable of driving large capacitances
Solution Approach 1:
The frequency divider is segmented into multiple stages (divide by 2 stage followed by another divide by 2 stage), allowing the use of lower frequency VCOs in each stage rather than requiring a single high frequency VCO. This segmentation reduces the power consumption while maintaining the overall divide by 4 functionality and receiver performance.
Solution Approach 2:
The patent employs dynamic sizing of transistors within the frequency divider circuit, where critical paths use larger transistors for speed while non-critical paths use smaller transistors to save power. This dynamic approach optimizes the balance between performance and power consumption across different operating conditions.
2Reliability
If larger devices are used for master latches to reduce phase noise, then phase noise is reduced, but device area increases
Solution Approach 1:
Different transistor sizes are applied to different parts of the frequency divider circuit based on their specific requirements. Master latches use larger devices to reduce phase noise, while slave latches and non-critical paths use smaller devices to minimize area. This local differentiation optimizes both phase noise performance and area utilization.
Solution Approach 2:
The frequency divider uses asymmetric latch design where master latches have different (larger) device sizes compared to slave latches. This asymmetry is intentional and optimized to reduce phase noise in the critical output paths while keeping the overall circuit area manageable through selective sizing.
Data Source
AI summary
In one embodiment, a local oscillator and mixer architecture may include a frequency divider having I and Q channel master storage elements formed of devices of a first size, and I and Q channel slave storage elements formed of devices of a second size, where the second size is smaller than the first size. In such manner, power consumption may be reduced while reducing phase noise in signals provided from the frequency divider to the corresponding mixer.