Frequency-Adaptive Delay-Locked Loop for Shorter Memory Lock Time
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Solution Overview
Problem
The locking time of delay locked loops (DLLs) in semiconductor memory devices increases power consumption and decreases overall performance, particularly in DDR memory systems, due to the reliance on fixed delay cells and initial select values that do not adapt to frequency changes.
Innovation Solution
A delay locked loop system that adjusts its initial select value based on the frequency of the operating clock, using a phase detector and control unit to determine and update the select value, ensuring the output clock is delayed by a consistent number of periods, thereby reducing locking time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed initial select value is used in the delay locked loop, then the device structure is simple, but the locking time increases and power consumption increases
Solution Approach 1:
The patent applies dynamics by making the initial select value adjustable rather than fixed. The DLL controller dynamically changes the initial select value based on the operating frequency of the input clock, allowing the delay line to adapt its initial state to different frequency conditions, thereby reducing locking time without excessive complexity
Solution Approach 2:
The patent changes the parameter of the initial select value based on the input clock frequency. By updating the initial select value according to frequency changes, the system optimizes the locking process for different operating conditions, reducing both locking time and power consumption while maintaining manageable device complexity
2Device complexity
If a fixed initial select value is used in the delay locked loop, then the device structure is simple, but power consumption increases
Solution Approach 1:
The patent makes the initial select value dynamic rather than static. The DLL controller adjusts the initial select value based on the input clock frequency, enabling the delay line to reach lock faster under different frequency conditions, which reduces the duration of high-power operation and thus lowers overall power consumption
Solution Approach 2:
The patent updates the initial select value parameter according to frequency changes. This adaptive approach allows the DLL to optimize its locking behavior for different operating frequencies, reducing unnecessary power consumption during the locking process while keeping the device structure relatively simple
3Loss of time
If the initial select value is adjusted according to frequency changes, then locking time is reduced and power consumption is reduced, but the device complexity increases
Solution Approach 1:
The patent implements dynamics by adding a DLL controller that adjusts the initial select value based on frequency detection. This dynamic adaptation reduces locking time across different frequency conditions while keeping the added complexity minimal through integrated control logic
Solution Approach 2:
The patent changes the initial select value parameter based on frequency information. By updating this parameter adaptively, the system achieves reduced locking time and power consumption with relatively modest increases in device complexity, as the control logic can be implemented within the existing DLL architecture
4Use of energy by moving object
If the initial select value is adjusted according to frequency changes, then power consumption is reduced, but the device complexity increases
Solution Approach 1:
The patent applies dynamics by making the initial select value frequency-dependent. The DLL controller dynamically adjusts this value based on the operating frequency, enabling faster locking and reduced power consumption without requiring major structural changes to the DLL
Solution Approach 2:
The patent updates the initial select value parameter according to frequency changes. This parameter adaptation allows the system to optimize power consumption across different operating conditions while maintaining relatively simple device architecture through integrated control logic
Data Source
AI summary
A delay locked loop (DLL) is provided. The DLL includes a delay line, a phase detector, a delay line control unit, and a DLL controller. The delay line outputs an output clock by delaying an input clock by a first time on the basis of a select value. The phase detector detects a phase of the output clock. The delay line control unit determines a select value so that the first time corresponds to n periods of the input clock on the basis of the detected phase and an initial select value. The DLL controller provides the initial select value to the delay line control unit. The DLL controller updates the initial select value according to a change of a frequency of the input clock, and to provide the updated initial select value to the delay line control unit.