Frequency Lock Loop Control for Stable DC-DC Switching Frequency
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Solution Overview
Problem
Existing DC-DC converters face challenges in maintaining a constant switching frequency due to parasitic losses and inefficiencies, with current methods failing to accurately regulate switching frequency variations caused by non-ideal components and systemic variables, leading to suboptimal power system design and increased electromagnetic interference.
Innovation Solution
A frequency lock loop (FLL) is integrated with the TON/TOFF generator to sense real-time switching activities and adjust the TON/TOFF width based on feedback signals, eliminating the need for complex circuits to compensate for systemic variables and ensuring stable switching frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If feed forward circuits are used to adjust TON/TOFF based on VIN, VOUT, ILOAD information, then some switching frequency variation is removed, but new FSW variations are introduced due to circuit accuracy and non-linearity problems
Solution Approach 1:
The patent implements a feedback mechanism where the actual switching frequency is monitored and used to adjust the TON/TOFF timing. A frequency detection circuit measures the actual FSW, and this information feeds back to modify the on-time/off-time periods dynamically, closing the control loop to eliminate frequency deviations caused by component variations and parasitic effects
Solution Approach 2:
The control system uses its own output (switching frequency) as input for correction. The frequency detection circuit monitors the converter's actual switching frequency, and this self-measured information is used to automatically adjust the TON/TOFF generator, making the system self-regulating without requiring external complex compensation circuits
2Measurement precision
If TON/TOFF is adjusted based on VIN, VOUT, ILOAD information, then switching frequency control is improved, but accuracy is insufficient due to comparator delay, dead time, and power stage losses
Solution Approach 1:
The patent employs feedback by detecting the actual switching frequency and using this information to correct TON/TOFF timing errors. The frequency detection circuit measures real switching events, and the feedback mechanism compensates for comparator delays and dead time effects by dynamically adjusting timing based on actual performance rather than relying on pre-calculated values
Solution Approach 2:
The system dynamically changes the TON and TOFF parameters based on detected switching frequency deviations. Rather than using fixed compensation values, the system continuously adjusts these timing parameters in response to actual switching events, adapting to varying load conditions, input voltage changes, and component tolerances
3Ease of operation
If constant on-time or constant off-time schemes are used to control output, then output regulation is achieved, but switching frequency varies more than 20% with different VIN, VOUT, and Load Current
Solution Approach 1:
The patent transitions from static constant on-time/off-time control to dynamic control by introducing frequency-based timing adjustment. The TON and TOFF periods are no longer fixed but are dynamically modified based on the detected switching frequency, allowing the system to maintain simple control operation while achieving frequency stability across varying operating conditions
Solution Approach 2:
The system uses feedback from frequency detection to regulate switching frequency while maintaining constant on-time/off-time control for output regulation. The detected frequency information feeds back to adjust timing parameters, enabling the system to simultaneously achieve both output control simplicity and frequency stability
Data Source
AI summary
A frequency lock loop for a constant switching frequency of DC-DC converter, wherein the frequency lock loop includes a modulation circuit to generate a modulation signal in response to an input signal of the DC-DC converter and a frequency signal. Wherein a timer of the DC-DC converter generates a timing signal in response to the input signal, and wherein the frequency signal is a function of the timing signal.