Frequency Multiplier Resonance Circuit for Size Reduction
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Solution Overview
Problem
Conventional frequency multipliers are large in size due to the need for separate circuits for fundamental wave suppression and impedance matching, making them difficult to miniaturize, especially when constructed on Si substrates for high-frequency applications.
Innovation Solution
A frequency multiplier design that incorporates a resonance circuit formed by a series connection of an inductor and a capacitor, coupled in parallel to a middle node, which suppresses the fundamental wave and matches impedance for harmonic signals, allowing for the transmission of n-time multiples of the input signal frequency while eliminating the fundamental signal component.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stub circuit with one-fourth wavelength of the fundamental wave is used for suppressing the fundamental wave, then the fundamental wave suppression is achieved, but the circuit size becomes large
Solution Approach 1:
The patent combines the fundamental wave suppression function and the impedance matching function into a single resonance circuit. The resonance circuit includes a series connection of an inductor and a capacitor, where the inductor has a specific inductance value and the capacitor has a specific capacitance value that together provide both the suppression of the fundamental wave and the matching of impedance for the n-time multiple waves, eliminating the need for separate stub circuit and impedance matching circuit
Solution Approach 2:
The resonance circuit is designed to perform multiple functions simultaneously: it suppresses the fundamental wave through its resonance characteristics while also providing impedance matching for the harmonic frequencies. This multi-functional design reduces the overall circuit complexity and size by replacing multiple dedicated circuits with a single integrated resonance circuit
2Reliability
If separate circuits are used for fundamental wave suppression and impedance matching, then each function is optimized, but the overall circuit size increases
Solution Approach 1:
The patent merges the suppression circuit and impedance matching circuit into a single resonance circuit. The resonance circuit comprises an inductor with inductance L and a capacitor with capacitance C connected in series, where the combination provides both the fundamental wave suppression through resonance and the impedance matching for harmonic frequencies, thereby reducing circuit complexity while maintaining functional optimization
3Ease of manufacture
If conventional frequency multiplier circuits are constructed on Si substrates, then integration is achieved, but the circuit size becomes excessively large
Solution Approach 1:
The patent integrates the fundamental wave suppression and impedance matching functions into a single resonance circuit that can be constructed on Si substrates. By combining these functions, the circuit size is reduced from 20 mm to a much smaller dimension, making it suitable for integrated circuit applications while maintaining the suppression and matching functions
Solution Approach 2:
The patent uses specific parameter values for the inductor (inductance L) and capacitor (capacitance C) in the resonance circuit to achieve both fundamental wave suppression and impedance matching in a compact size. The parameters are optimized to provide the desired frequency characteristics while minimizing the physical dimensions of the circuit components on the Si substrate
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the circuit size by integrating fundamental wave suppression and impedance matching within the resonance circuit, enabling efficient transmission of harmonic components and improving output power while maintaining a compact form factor.
Implementation Method 1
a resonance circuit that has a resonance frequency equal to a frequency of the input signal and that also has an impedance matching the predetermined input impedance of the output circuit
Implementation Method 2
a resonance circuit that is formed as a series connection of an inductor and a capacitor
Data Source
AI summary
A frequency multiplier includes an input circuit, an output circuit, and a resonance circuit. The input circuit is coupled to an input node and a middle node. The middle node provides a middle signal that has a signal component having the same frequency as an input signal that is provided to the input node. The middle signal further has an even number “n” multiple of the input signal frequency. The output circuit has a predetermined input impedance for the middle node. The resonance circuit includes an inductor that is coupled in series with a capacitor, where the capacitor is in a parallel connection to the middle node. The resonance circuit has a resonance frequency that is equal to a frequency of the input signal, and such resonance circuit also has an output impedance that matches with the predetermined input impedance of the output circuit.