Fringe-Induced Hole Injection for Charge Trapping Memory Operation Window
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Charge trapping memory devices face challenges in maintaining a large operation window and reducing the second bit effect due to charge accumulation and varying erase speeds, leading to poor endurance and increased difficulty in scaling down technology.
Innovation Solution
The implementation of a fringe-induced effect in charge trapping memory devices, where hole charges are stored along the fringes of word lines with a larger electrical field, allowing for a virtual ground array with distinct voltage thresholds, enabling efficient hole injection methods to expand the memory operation window and reduce the second bit effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge trapping memory devices use traditional erase methods with thick bottom oxide, then charge loss is prevented, but erase speed decreases and charge accumulation occurs
Solution Approach 1:
The patent segments the charge trapping memory cell into distinct regions with different oxide thicknesses: a thick bottom oxide region for charge retention and a thin bottom oxide region at the fringe for efficient hole injection. This spatial segmentation allows simultaneous achievement of both charge retention and fast erase speed
Solution Approach 2:
The patent applies local quality by creating a non-uniform oxide structure where the bottom oxide thickness varies across the cell. The fringe region has thin oxide (enabling fast hole injection) while the center region has thick oxide (ensuring charge retention), optimizing both erase speed and reliability in different locations
2Ease of operation
If sector erase is performed on charge trapping memory, then all cells are erased, but erase speed varies due to process variations causing large Vt distribution
Solution Approach 1:
The fringe-induced hole injection creates a localized high electric field region that dominates the erase process. This local quality approach ensures uniform erase behavior across all cells by making the erase process dependent on the controlled fringe geometry rather than on process variations in channel length
3Quantity of substance
If charge trapping memory stores 2 bits per cell, then storage capacity increases, but second bit effect increases reducing operation window
Solution Approach 1:
The patent segments the charge trapping layer into distinct storage regions: one region under the word line for the first bit and another region at the fringe for the second bit. This spatial segmentation reduces coupling between bits and minimizes the second bit effect, maintaining a large operation window for 2-bit storage
Solution Approach 2:
The fringe region acts as an intermediary that enables independent control of the second bit. By confining hole injection to the fringe region, the patent creates a mediator mechanism that allows the second bit to be programmed and erased independently from the first bit, reducing interference
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases program and erase efficiency and expands the second bit operation window, improving memory device performance and endurance by managing charge distribution and erase speed variability.
Implementation Method 1
the fringes of the word line have a larger electrical field relative to non-fringe areas of the word line
Implementation Method 2
holes are moved to the charge trapping layer by a hole injection, and positioned underneath and along the first and second fringes of the gate electrode
Data Source
AI summary
Charge trapping memory devices and methods are included for increasing a second bit operation window by a fringe-induced effect. The fringe-induced effect occurs in areas underneath a word line so that when a hole injection method is applied to a memory device, hole charges are stored in a charge trapping layer that intersects with a word line and the hole charges are stored along fringes of the word line. In one embodiment, a virtual ground array includes a charge trapping layer that is disposed between two dielectrics such that there is not a charge trapping layer over source and drain regions. After a hole injection is applied to the virtual ground array, hole charges are stored along fringes of each word line given the fringes of the word line has a larger electrical field relative to non-fringe areas of the word line.