Fringe Voltage Programming in NAND Flash Memory Cells

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Solution Overview

Problem

NAND type flash memory devices face reliability issues due to partial discharge of charges in floating gate patterns caused by high dielectric constant materials used in dielectric layers, leading to data loss and malfunctions.

Innovation Solution

The method involves applying a fringe voltage to a conductive layer pattern spaced apart from the floating gate, which generates a fringe field and increases the potential of the floating gate for programming, reducing the need for high programming voltages and minimizing charge trapping in the dielectric layer, thereby enhancing reliability and operational characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If a dielectric layer with high dielectric constant material is used to increase capacitance between floating gate and control gate, then the coupling ratio is improved, but charges in the floating gate are partially discharged through trap sites in the dielectric layer

Engineering Contradiction:

Improvecoupling ratioVSAvoidcharge retention

Core Design Contradiction:

Stability of the object's compositionVSReliability

Solution Approach 1:

The patent segments the dielectric layer into multiple layers with different materials and properties. The first dielectric layer uses high dielectric constant material for strong coupling, while the second dielectric layer uses low dielectric constant material to prevent charge discharge, effectively dividing the functions of charge storage and charge protection.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent employs a composite dielectric structure combining materials with different dielectric constants. This composite approach allows the system to simultaneously achieve high capacitance for programming efficiency and low charge trapping for data retention reliability, resolving the contradiction between coupling strength and charge stability.

Inventive Principle:

Principle #40Composite materials

2Manufacturing precision

If the floating gate pattern is made thin to reduce interference between adjacent patterns, then manufacturing precision is improved, but the capacitance between floating gate and control gate decreases

Engineering Contradiction:

Improveinterference reductionVSAvoidcapacitance

Core Design Contradiction:

Manufacturing precisionVSStability of the object's composition

Solution Approach 1:

The patent changes the dielectric constant parameter of the dielectric layer material to compensate for the reduced capacitance caused by thin floating gate structures. By using high dielectric constant material, the system maintains sufficient capacitance values even with reduced gate thickness, thereby preserving programming efficiency while allowing thinner gates for better manufacturing control.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If high programming voltage is applied to program data in the floating gate, then programming speed is improved, but more charges are trapped in the dielectric layer causing data loss

Engineering Contradiction:

Improveprogramming speedVSAvoiddata loss

Core Design Contradiction:

ProductivityVSLoss of information

Solution Approach 1:

The patent applies different dielectric properties to different regions/layers: the first dielectric layer near the floating gate uses high dielectric constant material to enable efficient charge transfer at lower voltages, while the second dielectric layer uses low dielectric constant material to minimize charge trapping. This local differentiation allows effective programming at reduced voltages, preventing charge loss while maintaining productivity.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for stable and reliable programming and erasing of data in NAND flash memory devices using lower voltages, reducing data loss and improving overall device performance.

Implementation Method 1

applying a fringe voltage to the conductive layer pattern to generate a fringe field in the floating gate

Methodology Applied

Scientific EffectFringe field generation: Electric Field

Implementation Method 2

a high capacitance may be provided between a floating gate pattern and a control gate pattern in the cell by using a metal oxide having a high dielectric constant for a dielectric layer

Methodology Applied

Scientific EffectDielectric constant: Dielectric Permittivity

Implementation Method 3

charges in the floating gate pattern may escape through the trap in the dielectric layer via an electric field between the floating gate pattern and the control gate pattern

Methodology Applied

Scientific EffectCharge trapping and discharge: Electric Field

Data Source

PatentUS7936600B2Methods of programming data in a non-volatile memory device with a fringe voltage applied to conductive layer

Publication Date: 2011.05.03 SAMSUNG ELECTRONICS CO LTD

AI summary

Methods of programming data in a non-volatile memory cell are provided. A memory cell according to some embodiments may include a gate structure that includes a tunnel oxide layer pattern, a floating gate, a dielectric layer and a control gate sequentially stacked on a substrate, impurity regions that are formed in the substrate at both sides of the gate structure, and a conductive layer pattern that is arranged spaced apart from and facing the floating gate. Embodiments of such methods may include applying a programming voltage to the control gate, grounding the impurity regions and applying a fringe voltage to the conductive layer pattern to generate a fringe field in the floating gate.