Free-Running Oscillator Clocking for PVT-Adaptive Multi-Core Domains
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Solution Overview
Problem
Integrated circuit design faces challenges in maintaining operation under varying process, voltage, and temperature (PVT) conditions, leading to inefficiencies and increased margins, especially with increasing processor counts and aging effects, where traditional synchronous clocking systems struggle to adapt.
Innovation Solution
Implementing a system of free running oscillators (FROs) that synchronize across a chip to adapt to PVT variations, ensuring the clock signal is determined by the worst-case region, allowing for flexible and asynchronous clocking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional synchronous clocking systems are used to maintain operation under varying PVT conditions, then reliability is improved, but device complexity and margin requirements increase
Solution Approach 1:
The chip is divided into multiple clock domains, each with its own free-running oscillator. This segmentation allows each domain to independently adapt to local PVT conditions while maintaining overall system reliability, eliminating the need for a single complex global clocking system that must account for all worst-case scenarios.
Solution Approach 2:
The clocking system transitions from a static synchronous approach to a dynamic asynchronous approach where each clock domain can operate at its own frequency. This dynamic adaptation allows the system to respond to changing PVT conditions in real-time, improving reliability without requiring excessive design margins.
2Reliability
If design margins are increased to ensure operation under worst-case PVT conditions, then reliability is improved, but productivity is reduced due to wasted clock period
Solution Approach 1:
Each clock domain is configured with local quality characteristics matched to its specific PVT conditions. Faster regions operate at higher frequencies while slower regions operate at lower frequencies, eliminating the need for all regions to operate at the conservative worst-case frequency. This local optimization maximizes clock period utilization in each domain while ensuring overall system reliability.
3Ease of operation
If a single central clock is used to synchronize the entire chip, then ease of operation is improved, but adaptability to PVT variations worsens
Solution Approach 1:
Each free-running oscillator provides feedback about its local PVT conditions through its operating frequency. This frequency information serves as a natural feedback signal that reflects the actual performance characteristics of each clock domain, enabling automatic adaptation without complex sensing and control circuitry.
Solution Approach 2:
Each clock domain is self-sufficient with its own free-running oscillator, eliminating dependence on a central clock. Each domain automatically adapts to its local conditions and maintains operation independently, providing both ease of operation within the domain and adaptability to PVT variations across the chip.
4Productivity
If the chip is designed for high operating frequency under nominal conditions, then productivity is improved, but reliability under worst-case PVT conditions worsens
Solution Approach 1:
The system transitions from a static design frequency to dynamic frequency adaptation. Each clock domain automatically adjusts its operating frequency based on actual PVT conditions, allowing regions to operate at high frequencies when conditions permit while maintaining reliability when conditions deteriorate. This eliminates the need to design for conservative worst-case frequencies across the entire chip.
Data Source
AI summary
A system of free running oscillators synchronized to the lowest frequency running one and following PVT variation generates a system clock. A method is particularly applicable to clock relatively small clock domains within a multi-core chip containing thousands of cores, and where the clock domain encompasses one or more cores and additional logic blocks. The resulting system clock is divided by 2k using latches or flip-flops to achieve a symmetric 50-50 duty cycle of the system clock. Further, such PVT insensitive system clock can be used as a reference for a PLL or DLL generated clock for the domain.