Front-to-Front Chip Interconnect Structure for Smaller Bonding Pitches
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing IC packaging technologies face challenges in further reducing density and improving performance as bonding pitches between RDL structures are too large, constraining further scaling and signal transmission speeds in vertically stacked ICs.
Innovation Solution
The implementation of interconnect structures that facilitate front-to-front stacking of chips with smaller bonding pitches, allowing direct bonding of frontside routing structures and the use of through vias to connect chips, reducing bonding pitches and enhancing signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing IC packaging technologies are used with RDL structures, then bonding pitches are maintained at current sizes, but device density cannot be further reduced and signal transmission speeds are limited
Solution Approach 1:
The patent transitions from conventional lateral bonding approaches to vertical stacking architecture, enabling chips to be stacked in the third dimension. This dimensional change allows multiple chips to be interconnected through through-via structures, achieving smaller effective bonding pitches and higher device density by utilizing vertical space rather than lateral expansion.
Solution Approach 2:
The patent divides the interconnection structure into multiple segments including through-vias penetrating chip substrates, intermediate bonding layers, and stacked chip modules. This segmentation enables independent optimization of each component and facilitates modular assembly, allowing bonding pitches to be reduced while maintaining manufacturability through standardized segment interfaces.
2Quantity of substance
If bonding pitches are reduced to increase device density, then more chips can be stacked, but manufacturing complexity and difficulty increase
Solution Approach 1:
The through-via structures serve multiple functions simultaneously: they provide electrical interconnection between stacked chips, act as mechanical support elements, and enable thermal management pathways. This multi-functionality reduces the need for separate specialized structures, thereby managing complexity while achieving high device density through vertical stacking.
Solution Approach 2:
The patent implements a nested structure where through-vias are embedded within chip substrates, which are then stacked and interconnected by bonding layers. Each chip module contains nested interconnect elements, and multiple modules are nested vertically. This nesting approach compactly integrates complex interconnection functions within reduced bonding pitch constraints.
3Speed
If conventional stacking methods are used, then current bonding pitch sizes are maintained, but signal transmission speeds are limited
Solution Approach 1:
By transitioning to vertical stacking with through-via interconnections, the patent shortens signal transmission paths in the lateral dimension while utilizing the vertical dimension for interchip communication. This dimensional reconfiguration reduces signal propagation distance and impedance, thereby increasing signal transmission speeds while enabling smaller bonding pitches through the vertical interconnection architecture.
Data Source
AI summary
Interconnect structures for front-to-front stacked chips/dies and methods of fabrication thereof are disclosed herein. An exemplary system on integrated circuit (SoIC) includes a first die that is front-to-front bonded with a second die, for example, by bonding a first topmost metallization layer of a first frontside multilayer interconnect of the first die to a second topmost metallization layer of a second frontside multilayer interconnect of the second die. A through via extends partially through the first frontside multilayer interconnect of the first die, through a device layer of the first die, through a backside power rail of the first die, and through a carrier substrate. The backside power rail is between the carrier substrate and the device layer, and the backside power rail may be a portion of a backside multilayer interconnect of the first die. The through via may be connected to a redistribution layer (RDL) structure.