Frontside-Backside Metal Interconnect for Low-RC Semiconductor Routing
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Solution Overview
Problem
Scaled technologies face challenges in back end of line (BEOL) design due to pin access and routing congestion, with high resistivity and capacitance in metal routing limiting IC performance, and the connection of frontside and backside metal layers requires a low-resistance path.
Innovation Solution
A method for connecting frontside and backside metal layers in semiconductor devices by forming conductive structures on both sides of the substrate, allowing for flexible optimization of metal RC through independent customization of metal pitch and thickness, using interconnection structures to link these layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If tight pitch is used for lower metal layers of F/S BEOL to increase routing density, then routing capacity is improved, but resistivity and capacitance increase due to shallow metal and proximity of metal layers
Solution Approach 1:
The patent transitions from two-dimensional planar routing to three-dimensional vertical routing by implementing backside metal layers. This allows signals to route vertically through the substrate, effectively adding a new dimension for signal paths and reducing the burden on frontside metal layers, thereby maintaining low resistivity while achieving high routing capacity.
Solution Approach 2:
The patent divides the metal routing system into separate frontside and backside segments. Each side can be independently optimized for its specific function, allowing the frontside to handle critical signal routing with larger pitch and the backside to provide additional routing capacity and power delivery without suffering from the same resistivity issues.
2Productivity
If tight pitch is used for lower metal layers of F/S BEOL to increase routing density, then routing capacity is improved, but capacitance increases due to proximity of metal layers
Solution Approach 1:
By introducing vertical routing through backside metal layers, the patent reduces the horizontal proximity of metal layers on the frontside. Signals can travel vertically through the substrate rather than being constrained to tight horizontal spacing, thereby reducing capacitive coupling between adjacent metal traces.
3Reliability
If B/S metal layers are used for flexible optimization of metal RC, then resistivity is reduced, but connection complexity increases between F/S and B/S metal
Solution Approach 1:
The patent introduces through-substrate vias as intermediary structures that automatically align and connect frontside and backside metal layers. These vias serve as mediators that simplify the connection process by providing predetermined, self-aligned pathways through the substrate, reducing the overall connection complexity despite adding backside metal layers.
4Ease of manufacture
If conventional F/S BEOL only is used for signal and power delivery network routing, then manufacturing process is simple, but IC performance is limited by BEOL resistivity
Solution Approach 1:
The patent segments the interconnect system into frontside and backside portions, each manufactured using conventional processes independently. This segmentation allows each side to be optimized for specific functions while maintaining manufacturing simplicity, as both sides can be processed using existing BEOL techniques without requiring entirely new manufacturing approaches.
Data Source
AI summary
The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device comprises a substrate, an isolation layer, a first electronic device, a first interconnection structure, a first conductive structure, and a second conductive structure. The substrate has a first surface and a second surface opposite the first surface. The isolation layer contacts the second surface of the substrate and has a first surface facing away from the substrate. The first electronic device is embedded in the substrate. The first interconnection structure extends from the first surface of the substrate to the first surface of the isolation layer. The first conductive structure is disposed on the first surface of the substrate. The second conductive structure contacts the first surface of the isolation layer. The first conductive structure and the second conductive structure are electrically connected by the first interconnection structure.