Frontside SEM Fault Isolation for SPR Semiconductor Inspection
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Solution Overview
Problem
Dynamic fault isolation of semiconductor chips with super power rail (SPR) structures is challenging due to obstructed access from the chip backside by power lines and packaging, making it difficult to perform chip analysis using optical instruments like laser scanning.
Innovation Solution
Perform chip dynamic fault isolation from the front side using scanning electron microscopy (SEM) with e-beam probing on metal layers in a vacuum chamber, integrated with automatic test equipment (ATE) for SPR chip scan dynamic fault isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If optical instruments like laser scanning are used for chip analysis from the backside, then the analysis can be performed on standard chips, but the method becomes inapplicable to chips with super power rail (SPR) structures where the backside is obstructed by power lines and packaging
Solution Approach 1:
The patent inverts the inspection approach by performing fault isolation from the front side of the chip instead of the traditional backside approach. The electron beam is directed at the front surface of the chip, and faults are detected by analyzing electrical signals returned through the interconnection structure, thereby avoiding the obstruction problem caused by backside power lines and packaging.
Solution Approach 2:
The patent replaces optical detection methods with electron beam-based scanning electron microscopy (SEM). Instead of using optical instruments that require direct optical access, the system uses an electron beam that can be directed at the front surface and detect faults through electrical signal analysis, substituting mechanical/optical detection with electron-beam-based detection.
2Measurement precision
If electron beam scanning is performed on the front side with electrical signal application, then fault detection capability is improved for obstructed chips, but the system complexity increases due to integration of SEM and ATE
Solution Approach 1:
The patent merges scanning electron microscopy (SEM) with automatic test equipment (ATE) into an integrated system. The SEM provides electron beam scanning and imaging capabilities while the ATE provides electrical signal generation and measurement capabilities. By combining these two systems, the patent achieves enhanced fault detection capability that leverages both structural imaging and electrical characterization.
Solution Approach 2:
The integrated SEM-ATE system performs multiple functions: it provides electron beam scanning for structural analysis, applies electrical signals for functional testing, measures returned electrical signals for fault detection, and generates comprehensive diagnostic data. This multi-functional system addresses both structural and electrical aspects of chip fault isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the ability to analyze SPR chips by improving process quality and facilitating effective fault detection through SEM e-beam probing on the front side, overcoming the limitations of backside access.
Implementation Method 1
directing an electron beam toward the frontside of the first semiconductor device
Data Source
AI summary
A method includes: providing a first semiconductor device including a backside interconnection structure, the first semiconductor device being formed by a semiconductor process; and generating a physical failure analysis model by an inspection process. The inspection process includes: directing an electron beam toward the frontside of the first semiconductor device; and applying an electrical signal to an electrical contact of the first semiconductor device through an electrical path that goes through a shunt board attached to a switchable interface trace bank, the electrical contact being associated with a position of the electron beam. The method further includes: generating a parameter of a revised semiconductor process according to the physical failure analysis model and the semiconductor process; and forming a second semiconductor device by the revised semiconductor process using the parameter.