Full Adder Circuit Using Transmission Gates for Lower Delay

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Solution Overview

Problem

Conventional Full Adder (FA) circuits suffer from high input capacitance, internal propagation delays, and performance degradation due to heavy transistor loading, especially in high-speed applications, and are not optimized for critical input states, leading to reduced reliability and increased latency.

Innovation Solution

A Full Adder (FA) circuit design comprising a Carry Output Generation (COG) circuit with inverter gates, AND gates, and an OR gate, and a Sum Generation (SG) circuit with cascaded transmission gates, optimized for fewer stages and transistors, using CMOS-based static logic to minimize input capacitance and enhance speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional FA circuits use multiple transistors and cascaded stages to implement adder logic, then the circuit can perform the required addition function, but the input capacitance increases and propagation delay increases

Engineering Contradiction:

Improvecircuit performanceVSAvoidtransistor count

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple transistor functions into fewer transistors by using transmission gates that can perform both switching and logic functions simultaneously. The SUM generation circuit uses transmission gates to merge the functionality of multiple stacked transistors into a single stage, reducing the overall transistor count while maintaining the adder's computational capability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent segments the adder circuit into distinct functional blocks: COG circuit for carry-out generation and SG circuit for sum generation. Each block is optimized independently with the COG circuit handling carry logic and the SG circuit handling sum logic, allowing for reduced complexity in each segment while maintaining overall functionality.

Inventive Principle:

Principle #1Segmentation

2Speed

If conventional FA circuits use heavy transistor loading to drive outputs, then the circuit can provide sufficient drive strength, but the internal propagation delay increases

Engineering Contradiction:

Improveoperation speedVSAvoidpropagation delay

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The patent uses preliminary signal inversion in the COG circuit where inputs are inverted before processing. This preliminary action prepares signals in advance to reduce the critical path delay in the main computation stage, allowing the circuit to achieve faster operation without increasing transistor loading.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If conventional FA circuits use stacked transistors to generate SUM output, then the logic function can be implemented, but the input capacitance and propagation delay increase

Engineering Contradiction:

Improvelogic function correctnessVSAvoidsignal propagation speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent replaces the mechanical stacking of transistors in series with transmission gate-based logic. Instead of using multiple transistors stacked vertically to achieve the XOR function for SUM generation, the invention uses transmission gates that can implement the same logic function with parallel signal paths, eliminating the speed penalty associated with stacked transistor configurations.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Use of energy by moving object

If conventional FA circuits are designed for low power consumption, then energy efficiency is improved, but the circuit speed and performance degrade

Engineering Contradiction:

Improvepower consumptionVSAvoidcircuit speed

Core Design Contradiction:

Use of energy by moving objectVSSpeed

Solution Approach 1:

The patent employs dynamic transmission gate switching that adapts to input conditions. The transmission gates are controlled to switch optimally based on the input states, providing low impedance paths only when needed for signal transmission. This dynamic behavior allows the circuit to maintain low power consumption during idle states while achieving high speed during active computation.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20250265039A1Full adder circuit and methods for high speed computing applications

Publication Date: 2025.08.21 SAMSUNG ELECTRONICS CO LTD

AI summary

A Full Adder (FA) circuit includes a Carry Output Generation (COG) circuit including a first set of inverter gates to generate inverted input signals, and AND gates connected to the first set of inverter gates to generate a first output signal from the inverted input signals. An OR gate is connected to the AND gates, and a second inverter gate is connected to the OR gate. The OR gate generates a second output signal from the first output signal, and the second inverter gate generates a Carry Output (CO) signal from the second output signal. A Sum Generation (SG) circuit is connected to the COG circuit. The SG circuit includes a first cascaded block of transmission gates to generate an output from the CO signal, and a second cascaded block of transmission gates connected to the output of the first cascaded block of transmission gates to generate an output SUM signal.