Full-Rate Write Interface for Hardware Emulation Data Arrays
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Solution Overview
Problem
Current simulation acceleration methods in electronic design automation (EDA) tools face inefficiencies due to the need for emulating virtual communications and routing logic, which wastes emulation resources and causes significant time delays in data routing between hardware components, leading to slower verification speeds and reduced emulation capacity.
Innovation Solution
A system and method that utilize a high-speed interface to directly write simulation acceleration data from a host workstation to a hardware emulation system's data array connected to the system bus, eliminating the need for intermediate emulations and reducing data transfer delays by using a high-speed interface like PCI Express and optimizing data array architecture for parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If virtual communications and routing logic are emulated in simulation acceleration, then communication between hardware components is enabled, but emulation resources are wasted and time delays increase
Solution Approach 1:
The patent extracts and removes the virtual communications and routing logic from the emulation system. By taking out these non-essential communication functions, the system eliminates the waste of emulation resources and time delays associated with emulating them, while maintaining the core simulation acceleration functionality.
Solution Approach 2:
The patent makes the emulation system universally compatible by allowing it to directly accept data from external sources (host workstation) without requiring dedicated virtual communication infrastructure. This multi-functionality enables the system to operate efficiently whether data comes from virtual sources or direct external connections.
2Reliability
If virtual communications logic is emulated, then data routing between hardware components is enabled, but data transfer delays increase
Solution Approach 1:
The patent removes the virtual communications logic that causes data transfer delays. By extracting this intermediate layer, data can be transferred directly from the host workstation to the emulation system without undergoing the additional routing and communication overhead that previously caused time delays.
Solution Approach 2:
The patent eliminates the need for virtual communication mediators by establishing a direct data path. Instead of using intermediate virtual communication logic to route data between hardware components, the system allows direct data transfer, removing the mediating layer that introduced delays.
3Productivity
If simulation acceleration data are written to data arrays, then verification speed is enhanced, but resource capacity is consumed
Solution Approach 1:
The patent extracts and removes the virtual communication infrastructure from the system. By taking out these unnecessary communication components, emulation resource capacity is freed up while maintaining the ability to write simulation acceleration data to data arrays at full rate, thus enhancing verification speed without proportionally consuming resources.
Data Source
AI summary
A system and method for writing simulation acceleration data from a host workstation to a hardware emulation system without considerably sacrificing emulation speed or sacrificing the emulation capacity available for a user's logic design. According to one embodiment, a system comprises a logic software simulator running on a host workstation; a hardware emulation system having a system bus and an emulator chip, the emulator chip includes: an emulation processor that generates emulation data, and a data array connected to the system bus; and a high-speed interface connecting the host workstation to the system bus of the hardware emulator, wherein simulation acceleration data from the host workstation are written to the data array of the emulator chip using the system bus.