Electric Fuse Cell Well Layout for Smaller Semiconductor Area
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Solution Overview
Problem
Existing semiconductor devices with electric fuse cells occupy a large planar area due to the spacing requirements between fuse cells, which increases the size of the trimming circuit and reduces efficiency.
Innovation Solution
The semiconductor device integrates a dielectric film on a semiconductor substrate with electric fuse portions, where a first well region connects under each fuse portion, reducing the distance between fuse cells and minimizing the planar occupation area by eliminating the need for a p-type impurity region between well regions, and using a shallow trench isolation structure with a dielectric film to suppress dishing during chemical mechanical polishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional electric fuse cell configurations are used with separate well regions under each fuse portion, then each fuse cell can be independently formed, but the planar occupation area increases due to spacing requirements between fuse cells
Solution Approach 1:
Multiple separate well regions under different electric fuse portions are merged into a single continuous first well region that extends beneath multiple fuse cells. This consolidation eliminates the need for spacing between individual well regions, thereby reducing the overall planar occupation area while maintaining proper electrical isolation through the dielectric film for reliable fuse detection.
Solution Approach 2:
The well region structure transitions from discrete, separated regions in the planar dimension to a continuous extended region that utilizes the vertical dimension and spans across multiple fuse cell locations. This dimensional reorganization allows closer spacing of fuse cells while maintaining electrical isolation through the dielectric film layer.
2Area of stationary object
If larger spacing is provided between electric fuse cells, then manufacturing and detection reliability improves, but the planar occupation area and device size increase
Solution Approach 1:
Adjacent well regions are merged into a continuous first well region that provides uniform electrical characteristics across multiple fuse cells. This consolidation reduces the cumulative dimension variations that would arise from multiple separate well region interfaces, thereby improving manufacturing precision while minimizing the required spacing between fuse cells.
Solution Approach 2:
The dielectric film is selectively positioned in specific local regions between fuse cells to provide necessary electrical isolation, while allowing the well regions to continue continuously underneath. This localized application of isolation structures maintains manufacturing precision without requiring excessive spacing across the entire device area.
Data Source
AI summary
The dielectric film IF is disposed on the semiconductor substrate SB, and the plurality of electric fuse portions FU are disposed on the dielectric film IF. The n-type first well region WL1 is disposed in the semiconductor substrate SB and on the surface of the semiconductor substrate SB. The first well region WL1 is formed by integrally connecting the well region WLa located under each of the plurality of electric fuse portions FU to each other.