Fuse Structure With Spare Array Isolation for Post-Assembly Repair
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Solution Overview
Problem
Detecting and repairing weak bits in memory devices after assembly is challenging due to the difficulty in obtaining high voltage for blowing fuses, especially when the devices are mounted on a printed circuit board.
Innovation Solution
A semiconductor device design incorporating a doped structure, dielectric layers, and insulating structures with fuses that allow for the creation of high voltage and high current paths without affecting the main array, enabling post-assembly testing and repair.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the memory device is assembled and mounted on a printed circuit board, then the device achieves miniaturization and integration, but it becomes difficult to obtain high voltage for blowing fuses for testing and repair
Solution Approach 1:
The semiconductor device is divided into a main array and a spare array that can be independently activated. The spare array serves as a dedicated testing and repair subsystem that can generate high voltage without affecting the main operational array, enabling fuse blowing operations after assembly while maintaining device miniaturization.
Solution Approach 2:
A high voltage generating circuit is introduced as an intermediary component within the spare array. This circuit acts as a mediator that creates the necessary high voltage conditions for fuse blowing and testing operations, bridging the gap between the assembled device state and the repair requirements.
2Ease of repair
If a spare array is isolated to create high voltage paths for repair, then post-assembly testing becomes possible, but the device structure becomes more complex
Solution Approach 1:
The spare array shares common structural elements and fabrication processes with the main array, merging design principles to reduce overall complexity. While functionally isolated, the spare array utilizes similar transistor structures, interconnect layers, and manufacturing steps, thereby limiting the increase in device complexity while enabling post-assembly testing capabilities.
Data Source
AI summary
A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a fuse metal, a doped structure, a first dielectric layer, a second dielectric layer and two doped portions. The first dielectric layer extends along a first direction and disposed above the fuse metal. The first dielectric layer includes a first recess structure for accommodating the fuse metal. The doped structure is formed above the first dielectric layer and extends along a second direction vertical to the first direction. The second dielectric layer extends along the first direction and is disposed above the doped structure. The doped portions are adjacent to two lateral surfaces of the doped structure, and the doped portions are spaced apart from the first dielectric layer and the second dielectric layer.