PC-relative load store addressing for fused instructions
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Solution Overview
Problem
In modern information and data handling systems, out-of-order instruction execution and pipelining lead to processor latency and inefficiency due to the complexity of handling instructions, particularly when dealing with multiple execution units and dependencies between instructions.
Innovation Solution
A method and system where two consecutive instructions, a prefix and a suffix, are fused into a single instruction, allowing them to be executed together, with the prefix instruction being auto-finished and the suffix instruction being executed using operands formed based on the current instruction address, thereby improving processor efficiency and reducing execution time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If instructions are processed using traditional pipelining and out-of-order execution, then processor can handle multiple instructions concurrently, but processor latency and inefficiency increase due to complexity of handling dependencies between instructions
Solution Approach 1:
The patent merges a prefix instruction and a suffix instruction into a single fused instruction that can be executed atomically. This combining eliminates the need to handle them as separate instructions with potential dependencies, reducing latency while maintaining concurrent execution capability. The fused instruction is treated as a single unit in the issue queue and execution pipeline.
2Speed
If multiple execution units are used to process instructions in parallel, then processing speed increases, but device complexity increases due to handling multiple execution units and instruction dependencies
Solution Approach 1:
By fusing the prefix and suffix instructions into a single instruction entity, the patent reduces the complexity of managing multiple independent instructions. The fused instruction is dispatched as one unit to the appropriate execution unit, simplifying the control logic for handling dependencies and reducing the state management burden in the issue queue and rename/allocate units.
3Adaptability or versatility
If prefix and suffix instructions are executed as separate instructions, then instruction flexibility is maintained, but execution time increases due to sequential processing requirements
Solution Approach 1:
The fusion of prefix and suffix instructions into a single atomic operation allows both instructions to be executed simultaneously rather than sequentially. The prefix instruction's operations (such as address calculation) and the suffix instruction's operations (such as load/store) are performed in parallel as part of the same fused instruction execution, reducing total execution time while preserving the functional flexibility of having both instruction types.
Data Source
AI summary
Load store addressing can include a processor, which fuses two consecutive instruction determined to be prefix instructions and treats the two instructions as a single fused instruction. The prefix instruction of the fused instruction is auto-finished at dispatch time in an issue unit of the processor. A suffix instruction of the fused instruction and its fields and the prefix instruction's fields are issued from an issue queue of the issue unit, wherein an opcode of the suffix instruction is issued to a load store unit of the processor, and fields of the fused instruction are issued to the execution unit of the processor. The execution unit forms operands of the suffix instruction, at least one operand formed based on a current instruction address of the single fused instruction. The load store unit executes the suffix instruction using the operands formed by the execution unit.