Fused Reservation Stations Structure for Microprocessor Dispatch
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Solution Overview
Problem
Conventional reservation stations in microprocessors are inefficient and lack improved performance, leading to timing and throughput issues due to their complex design and inability to effectively manage instruction dispatching.
Innovation Solution
A fused reservation stations structure is introduced, comprising a primary and secondary RS with a bypass system, allowing for direct dispatch of instructions from the primary RS when the secondary RS is full, and utilizing a shift buffer to maintain instruction order, thereby reducing reissue delays and improving buffering efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional single reservation station structure is used, then the device complexity is reduced, but the throughput and timing performance deteriorate
Solution Approach 1:
The reservation station is divided into two separate structures: a first reservation station that receives instructions in program order and a second reservation station that dispatches instructions to execution units. This segmentation allows each station to be optimized for its specific function, improving overall throughput while keeping individual station complexities manageable.
Solution Approach 2:
The patent introduces a dual-reservation station architecture that adds a dimensional aspect to the instruction flow. Instructions can flow through different paths (direct dispatch or via the second reservation station), creating multiple dimensions for instruction processing and improving timing performance.
2Loss of time
If the reservation station is made smaller to improve timing, then the timing performance improves, but the ability to maintain instruction pool and parallelism deteriorates
Solution Approach 1:
The first reservation station performs preliminary actions by receiving and holding instructions in program order before they are dispatched to the second reservation station. This preliminary buffering ensures that instructions are ready for dispatch when execution units become available, maintaining instruction parallelism without requiring a large single reservation station.
Solution Approach 2:
The first reservation station acts as an intermediary between the instruction fetch unit and the second reservation station. It buffers instructions temporarily, allowing the system to maintain a sufficient instruction pool for parallelism while keeping the critical path timing short.
3Productivity
If a single reservation station is used, then the device complexity is low, but the dispatching efficiency and execution unit support deteriorate
Solution Approach 1:
The reservation station functionality is segmented into two specialized units: the first reservation station focuses on receiving and ordering instructions, while the second reservation station focuses on dispatching to execution units. This segmentation improves dispatching efficiency by allowing each unit to be optimized for its specific task.
Solution Approach 2:
The dual reservation station structure provides multi-functionality: the first station handles instruction reception and initial buffering, the second station handles dispatching to multiple execution units, and together they provide both ordering and out-of-order execution capabilities.
4Productivity
If conventional reservation station configuration is used, then the device complexity is reduced, but the entry efficiency and execution unit support deteriorate
Solution Approach 1:
The entry function is segmented and dedicated to the first reservation station, which is optimized for receiving instructions in program order with high entry efficiency. This separates the entry function from the dispatch function, allowing each to be optimized independently.
Data Source
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AI summary
A microprocessor with a fused reservation stations (RS) structure including a primary RS, a secondary RS, and a bypass system. The primary RS has an input for receiving issued instructions, has a push output for pushing the issued instructions to the secondary RS, and has at least one bypass output for dispatching issued instructions that are ready for dispatch. The secondary RS has an input coupled to the push output of the primary RS and has at least one dispatch output. The bypass system selects between the bypass output of the primary RS and at least one dispatch output of the secondary RS for dispatching selected issued instructions. The primary and secondary RS may each be selected from different RS structure types. A unify RS provides a suitable primary RS, and the secondary RS may include multiple queues. The bypass output enables direct dispatch from the primary RS.