Fused Shift/Logical Circuit for Single-Cycle Processor Operations
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Solution Overview
Problem
Conventional processors face challenges in executing shift and logical operations efficiently, as barrel shifters incur significant gate delay and require multiple processor clock cycles, hindering faster processing performance.
Innovation Solution
The implementation of a shift/logical circuit in processor devices that performs fused shift and logical operations within a single processor clock cycle without modifying the underlying instruction set architecture, utilizing a barrel shifter circuit and data reversal multiplexers to execute adjacent shift and logical instructions or instructions with embedded shift operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional barrel shifters are used to perform shift operations, then shift operations can be performed in a single processor clock cycle, but significant gate delay is incurred and processor performance is hindered
Solution Approach 1:
The patent combines shift operations and logical operations into a single fused operation executed by a unified shift/logical circuit. This merging eliminates the need for separate execution stages, allowing both operation types to complete in one processor clock cycle rather than requiring multiple sequential cycles, thereby reducing execution time and improving processor performance.
Solution Approach 2:
The shift/logical circuit is designed to perform multiple functions: it can execute shift operations (arithmetic shift left, arithmetic shift right, logical shift left, logical shift right), rotate operations (rotate left, rotate right), and logical operations (AND, OR, XOR, NOT). This multi-functional circuit replaces what would traditionally require separate dedicated circuits for each operation type, reducing overall gate delay and improving speed.
2Reliability
If separate shift instructions and logical instructions are executed sequentially, then instruction accuracy is maintained, but execution time increases
Solution Approach 1:
The fused shift/logical circuit merges the execution of shift and logical operations into a single unified operation. The circuit accepts source operands, performs the shift operation first, then immediately applies the logical operation to the shifted result within the same clock cycle, maintaining instruction accuracy while doubling execution throughput compared to sequential execution.
Solution Approach 2:
The shift operation is performed as a preliminary action within the fused circuit before the logical operation is applied. This preliminary shift execution prepares the data in the correct form for the subsequent logical operation, ensuring accuracy is maintained while both operations complete in a single clock cycle rather than requiring two separate cycles.
Data Source
AI summary
Performing fused shift and logical operations in processor-based devices is disclosed herein. In some aspects, a processor device comprises an instruction processing circuit that includes a shift/logical circuit. The instruction processing circuit is configured to detect, in an instruction stream, one or more instructions to perform a shift operation and a subsequent logical operation. In response to detecting the one or more instructions, the instruction processing circuit is further configured to use the shift/logical circuit to perform the shift operation and the logical operation in a single processor clock cycle.