Fusing Opposite Conditional Write Instructions to Eliminate Pipeline Hazards
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Solution Overview
Problem
In pipelined CPU architectures, the issuance of unnecessary or redundant instructions and pipeline hazards, such as read-after-write hazards, can hinder CPU performance by causing stalls and reducing throughput.
Innovation Solution
An instruction processing circuit that detects conditional write instructions with opposite conditions and generates a fused instruction, selecting one condition and value as 'if-true' and the other as 'if-false' based on the fused condition, to avoid redundant instructions and eliminate read-after-write hazards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conditional write instructions are issued sequentially to handle different conditions, then completeness of condition coverage is improved, but CPU throughput deteriorates due to redundant instructions and pipeline hazards
Solution Approach 1:
The patent combines multiple conditional write instructions with opposite conditions into a single fused instruction. The instruction processing circuit detects when two conditional write instructions target the same register with opposite conditions (e.g., EQ/NE, GT/LE), merges them into one fused conditional write instruction that contains both possible write operations, and executes them atomically. This eliminates redundant instructions and prevents read-after-write hazards while maintaining complete condition coverage.
2Reliability
If the CPU stalls to resolve read-after-write hazards, then correctness of instruction execution is improved, but execution time deteriorates
Solution Approach 1:
The instruction processing circuit performs preliminary detection and fusion of conditional write instructions with opposite conditions before they are executed. By identifying and merging these instructions in advance, the circuit ensures that only one fused instruction is issued to the execution pipeline, eliminating the need for stalls to resolve read-after-write hazards. The fused instruction is designed to atomically handle both conditions, ensuring correctness while maintaining continuous pipeline flow.
Data Source
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AI summary
Fusing conditional write instructions having opposite conditions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first conditional write instruction writing a first value to a target register based on evaluating a first condition is detected by an instruction processing circuit. The circuit also detects a second conditional write instruction writing a second value to the target register based on evaluating a second condition that is a logical opposite of the first condition. Either the first condition or the second condition is selected as a fused instruction condition, and corresponding values are selected as if-true and if-false values. A fused instruction is generated for selectively writing the if-true value to the target register if the fused instruction condition evaluates to true, and selectively writing the if-false value to the target register if the fused instruction condition evaluates to false.