GAA Transistor Backside Power Routing for Lower RC Delay

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Solution Overview

Problem

The increasing complexity and power dissipation issues in semiconductor integrated circuits (ICs) due to smaller geometry sizes and denser metal lines lead to reduced processing efficiency and performance, particularly in routing and RC delay, necessitating improved isolation structures and metal line routing methods.

Innovation Solution

The implementation of gate-all-around (GAA) transistor structures with improved isolation and a metal line routing method where power conductive vias are moved to the wafer back-side, utilizing the source/drain region as a power conductor path to reduce routing loading and logic cell area, and enhancing the connection between source/drain regions and power supply voltage lines through optimized contact areas.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If geometry size is decreased and functional density is increased, then production efficiency is improved and costs are lowered, but power dissipation increases and routing loading increases

Engineering Contradiction:

Improveproduction efficiencyVSAvoidpower dissipation

Core Design Contradiction:

ProductivityVSLoss of energy

Solution Approach 1:

The patent moves power conductive vias from the front side to the back side of the wafer, utilizing the third dimension (wafer thickness) to resolve the routing congestion problem. This dimensional change allows power delivery without increasing planar routing loading, thereby maintaining production efficiency while reducing power dissipation issues.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The source/drain region acts as an intermediary power conductor path between the back-side power conductive vias and the front-side power supply voltage lines. This intermediary structure enables efficient power transfer while reducing routing loading on the metal lines, addressing both productivity and power dissipation concerns.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Quantity of substance

If metal lines are made denser to increase functional density, then more circuits fit on chip area, but RC delay increases and processing efficiency decreases

Engineering Contradiction:

Improvenumber of interconnected devices per chip areaVSAvoidRC delay

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

By moving power conductive vias to the back side of the wafer, the patent eliminates the need for dense power routing on the front side metal layers. This dimensional relocation reduces the density of current-carrying paths, thereby reducing RC delay while maintaining high functional density through efficient power delivery via the source/drain intermediary path.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Reliability

If power conductive vias are placed on the front side, then connection to power supply is achieved, but routing loading increases and logic cell area increases

Engineering Contradiction:

Improveconnection between power supply and source/drainVSAvoidlogic cell area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent inverts the conventional approach by placing power conductive vias on the back side of the wafer instead of the front side. This inversion allows power delivery without occupying front-side routing resources, thereby reducing logic cell area while maintaining reliable power connection through the source/drain intermediary path to front-side power supply voltage lines.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The source/drain region serves as an intermediary that connects back-side power conductive vias to front-side power supply voltage lines. This intermediary structure enables reliable power connection without requiring front-side power conductive vias, thereby reducing logic cell area while maintaining connection reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Reliability

If contact area between power supply voltage lines and source/drain regions is increased, then connection reliability is improved, but more manufacturing processes are required

Engineering Contradiction:

Improvecontact resistanceVSAvoidnumber of manufacturing processes

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The source/drain region acts as an intermediary that provides a large effective contact area between back-side power conductive vias and front-side power supply voltage lines. This intermediary approach improves contact reliability without requiring additional manufacturing processes, as the source/drain region is already formed as part of the transistor structure.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20240170535A1Semiconductor structure and manufacturing method thereof

Publication Date: 2024.05.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes forming a transistor comprising a channel region, a gate structure surrounding the channel region, and a plurality of source/drain regions on opposite sides of the gate structure; forming a front-side contact on a front-side of one of the source/drain regions; forming a back-side conductive via below the one of the source/drain regions, wherein the front-side contact further downwardly extends from the front-side of the one of the source/drain regions to the back-side conductive via; forming a back-side power supply voltage line connecting to the back-side conductive via.