Gate-All-Around Channel Capping for Backside Power Rail Isolation
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Solution Overview
Problem
Conventional integrated circuits face increased voltage drop and power consumption as they scale down, with existing semiconductor fabrication methods inadequately addressing the need for efficient backside power rails and isolation from frontside components.
Innovation Solution
The implementation of backside power rails and self-aligned vias in semiconductor devices, along with specific fabrication methods that include forming a stack of semiconductor layers, patterning fins, and creating dielectric features to isolate backside power rails from frontside metal gates, enhances power rail resistance and reduces leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power rails are placed above transistors in conventional stacked-up fashion, then connectivity is provided to transistors, but voltage drop increases and power consumption increases as circuits scale down
Solution Approach 1:
The patent moves power rails from the conventional planar position above transistors to a backside power rail configuration, utilizing the third dimension (vertical stacking) and the backside of the substrate. This dimensional change allows power rails to be positioned below the transistor channel, reducing the current path length and associated voltage drop while improving power delivery efficiency.
Solution Approach 2:
The patent inverts the conventional power rail placement by positioning power rails on the backside of the substrate rather than above the transistors. This inversion reconfigures the current flow path and reduces the resistance and voltage drop associated with traditional power rail positioning, thereby reducing power consumption.
2Reliability
If backside power rails are implemented, then power rail resistance is reduced, but isolation from frontside components such as metal gates must be achieved
Solution Approach 1:
The patent introduces dielectric features as intermediary structures between the backside power rails and the frontside transistor channels. These dielectric features act as isolation barriers that prevent electrical interference and leakage between the power rails and active devices, enabling the backside power rail configuration without compromising device performance.
Solution Approach 2:
The patent segments the device structure into distinct functional regions: frontside active devices, backside power rails, and intermediate dielectric isolation layers. This segmentation allows independent optimization of each region while maintaining proper electrical isolation, reducing power rail resistance without compromising device functionality.
3Productivity
If conventional fabrication methods are used, then manufacturing process is simple, but gate density increases and device integration improves with backside power rails
Solution Approach 1:
The patent incorporates dielectric features and isolation structures during the early stages of fabrication, before final device assembly. This preliminary action ensures that isolation structures are already in place when backside power rails are formed, simplifying the overall manufacturing process while enabling higher gate density through effective backside power rail implementation.
Data Source
AI summary
A semiconductor device includes a first interconnect structure and multiple channel layers stacked over the first interconnect structure. A bottommost one of the multiple channel layers is thinner than rest of the multiple channel layers. The semiconductor device further includes a gate stack wrapping around each of the channel layers except a bottommost one of the channel layers; a source/drain feature adjoining the channel layers; a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature; and a dielectric feature under the bottommost one of the channel layers and directly contacting the first conductive via.