GAA Nanosheet Channel Etch Modulation for Uniform Channel Length

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Solution Overview

Problem

The integration of gate-all-around field effect transistor (GAA FET) devices faces challenges due to extruding end portions of channel layers, which cause non-uniformity and increased channel resistance, leading to degraded chip performance.

Innovation Solution

An etch rate modulation is applied by implanting etch rate modifying species into the channel layers, combined with a selective etching process to shrink the extruding end portions, improving channel length uniformity and reducing resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If an etching process is used to form source/drain trenches in stacked nanosheet GAA process flow, then source/drain regions can be formed, but extruding end portions of channel layers are created causing non-uniformity and increased channel resistance

Engineering Contradiction:
Improvesource/drain trench formationVSAvoidchannel length uniformity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming a sacrificial layer pattern before the source/drain trench etching process. This sacrificial layer pattern acts as a pre-established structure that guides the etching process to stop at the correct position, preventing the extrusion of channel layer end portions. The sacrificial layer is strategically positioned to define the boundary between the source/drain region and the channel region, ensuring uniform channel lengths are maintained during the trench formation process.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If an etching process is used to form source/drain trenches in stacked nanosheet GAA process flow, then source/drain regions can be formed, but extruding end portions of channel layers increase channel resistance

Engineering Contradiction:
Improvesource/drain trench formationVSAvoidchannel resistance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The sacrificial layer pattern is formed in advance to define the precise location where source/drain trenches should be etched. This preliminary structure ensures that the etching process does not extend into the channel region, thereby preventing the formation of extruding end portions that would increase channel resistance. The sacrificial layer acts as a protective barrier that maintains the integrity of the channel region during source/drain formation.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If gate-all-around structure is implemented to improve gate control, then gate-channel coupling is increased, but integration becomes challenging due to extruding channel layer ends

Engineering Contradiction:
Improvegate controlVSAvoidintegration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The sacrificial layer pattern is established before the complex gate-all-around structure formation process. This preliminary structure simplifies the integration by providing clear boundaries for subsequent processing steps. The sacrificial layer guides the formation of the gate structure around the channel, ensuring that the gate properly surrounds the channel region without being disrupted by extruding channel ends, thus maintaining gate control while reducing integration complexity.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively enhances channel length uniformity and reduces channel resistance, thereby improving the performance of GAA FET devices.

Implementation Method 1

An etch rate modulation is applied by implanting etch rate modifying species into the end portions of the channel layers

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS20240258407A1Multi-gate devices and fabricating the same with etch rate modulation
Publication Date: 2024.08.01 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240258407A1 patent drawing
  • US20240258407A1 patent drawing
  • US20240258407A1 patent drawing

AI summary

The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members vertically stacked above a substrate, a gate structure engaging the channel members, a gate sidewall spacer disposed on a sidewall of the gate structure, an epitaxial feature abutting end portions of the channel members, and inner spacers interposing the gate structure and the epitaxial feature. The end portion of at least one of the channel members includes a first dopant. A concentration of the first dopant in the end portion of the at least one of the channel members is higher than in a center portion of the at least one of the channel members. The concentration of the first dopant in the end portion of the at least one of the channel members is higher than in an outer portion of the epitaxial feature.