GAA Nanosheet Channel Thickness Layout for Higher Drive Current
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in optimizing channel thicknesses to enhance driving currents and device performance, particularly in gate all around (GAA) transistor structures, as conventional methods struggle to create pitches smaller than what is achievable with single photolithography processes.
Innovation Solution
The implementation of multi-gate devices with channel layers of varying thicknesses, specifically using epitaxial layers with different thicknesses, such as SiGe and Si, allows for the formation of nanosheet channels with tuned thicknesses, enabling precise control of channel lengths and widths through double-patterning or multi-patterning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional single photolithography processes are used, then manufacturing simplicity is maintained, but pitch size cannot be reduced below a certain limit
Solution Approach 1:
The patterning process is divided into multiple sequential steps (double-patterning or multi-patterning) where each step creates a portion of the final pattern. This segmentation allows achieving smaller pitch sizes that cannot be obtained with single photolithography, while managing complexity through systematic process breakdown
Solution Approach 2:
The patent introduces additional processing dimensions beyond single photolithography by implementing multiple patterning steps, including intermediate steps such as mandrel formation, spacer deposition, and selective etching. This dimensional expansion of the patterning process enables sub-lithographic pitch sizes
2Productivity
If channel layers with varying thicknesses are implemented, then driving currents and device performance are enhanced, but manufacturing precision requirements increase
Solution Approach 1:
Different channel layers are assigned different thicknesses based on their specific functional requirements. The patent forms channel layers with varying thicknesses (e.g., first channel layer with thickness T1, second channel layer with thickness T2) to optimize local electrical characteristics and driving currents for different device regions
Solution Approach 2:
The patent systematically varies the thickness parameter of channel layers to achieve desired electrical performance. By controlling deposition conditions and etch parameters, the manufacturing process achieves precise thickness control despite the complexity of multi-layer formation
3Length of moving object
If multi-patterning processes are used, then smaller pitch sizes are achieved, but manufacturing time and process complexity increase
Solution Approach 1:
Mandrel structures and spacer layers are formed in advance before final pattern transfer. These preliminary structures serve as templates for subsequent etching steps, enabling precise pattern definition while streamlining the overall manufacturing sequence
Solution Approach 2:
Intermediate spacer layers and mandrel structures act as mediators between the photolithography step and the final pattern. These intermediary elements enable the transfer of patterns at dimensions smaller than the direct lithographic resolution, reducing the need for excessive refinement steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances driving currents and device performance by allowing for the creation of GAA transistors with optimized channel structures, improving efficiency and reducing operational costs through advanced patterning techniques.
Implementation Method 1
The implementation of multi-gate devices with channel layers of varying thicknesses, specifically using epitaxial layers with different thicknesses, such as SiGe and Si
Data Source
AI summary
A device includes a first channel layer, a second channel layer, a gate structure, a source/drain epitaxial structure, and a source/drain contact. The first channel layer and the second channel layer are arranged above the first channel layer in a spaced apart manner over a substrate. The gate structure surrounds the first and second channel layers. The source/drain epitaxial structure is connected to the first and second channel layers. The source/drain contact is connected to the source/drain epitaxial structure. The second channel layer is closer to the source/drain contact than the first channel layer is to the source/drain contact, and the first channel layer is thicker than the second channel layer.