GAA Nanostructure Contact Layout for Lower Contact Resistance

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Solution Overview

Problem

The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to issues with processing and manufacturing complexity.

Innovation Solution

The process involves forming fin structures and gate all-around (GAA) transistor structures using photolithography and self-aligned double-patterning or multi-patterning techniques, with sacrificial layers and spacer formation to create patterns with smaller pitches, followed by epitaxial growth and metal gate stack formation to enhance device performance and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process complexity and difficulty increase

Engineering Contradiction:
Improveproduction efficiencyVSAvoidfabrication process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The fabrication process is divided into multiple patterning steps (self-aligned double-patterning or multi-patterning) where each step creates a portion of the final pattern. This segmentation allows complex small-pitch structures to be built through manageable sequential steps rather than attempting to create them in a single step, thereby maintaining productivity while managing fabrication complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Sacrificial layers are formed in advance before the final pattern is created. These preliminary structures serve as templates or masks for subsequent patterning steps, enabling precise feature formation at small dimensions while simplifying the overall fabrication process by pre-establishing critical alignments.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If contact area is increased to reduce contact resistance, then device performance improves, but fabrication complexity increases

Engineering Contradiction:
Improvedevice performanceVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The contact structure transitions from a simple planar contact to a three-dimensional wraparound contact that extends along the sidewalls of the fin structure. This dimensional change increases the contact area and reduces contact resistance without requiring proportionally more complex fabrication, as the additional contact area is achieved through vertical extension rather than lateral expansion.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The contact structure is formed by nesting multiple material layers (conductive layers, barrier layers, etch stop layers) around the fin structure, similar to nested dolls. This nested configuration allows the contact to wrap around the fin from multiple sides, maximizing contact area while using a systematic layer-by-layer fabrication approach that manages complexity.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the creation of semiconductor devices with improved performance and reliability by increasing the contact area and reducing contact resistance, while maintaining the complexity of the fabrication process manageable.

Implementation Method 1

followed by epitaxial growth and metal gate stack formation

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS11855215B2Semiconductor device structure with high contact area
Publication Date: 2023.12.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11855215B2 patent drawing
  • US11855215B2 patent drawing
  • US11855215B2 patent drawing

AI summary

A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor nanostructure and a second semiconductor nanostructure stacked over a substrate. The semiconductor device structure also includes a first epitaxial structure connecting the first semiconductor nanostructure and a second epitaxial structure connecting the second semiconductor nanostructure. The semiconductor device structure further includes a gate stack wrapped around the first semiconductor nanostructure and the second semiconductor nanostructure. In addition, the semiconductor device structure includes a conductive contact electrically connected to the epitaxial structures. The conductive contact has a portion extending towards the gate stack from terminals of the first epitaxial structure and the second epitaxial structures. The first epitaxial structure is wider than the portion of the conductive contact.