Gate-All-Around Cut Gate Layout With Self-Aligned Spacer Bridging
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Solution Overview
Problem
The scaling of multi-gate and nanowire transistors in integrated circuits poses challenges in maintaining mobility and short channel control, particularly due to constraints on lithographic processes, which affect critical dimension and spacing between features, leading to trade-offs in device performance and density.
Innovation Solution
The implementation of a pre-spacer-deposition cut gate approach, where a narrow poly cut is formed after hardmask patterning or poly etch, allowing for bridging with spacer deposition, enabling precise and cost-effective patterning of narrow and wide poly cuts, and facilitating self-aligned gate endcap structures for improved transistor density and strain maintenance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to pattern transistor features, then manufacturing simplicity is maintained, but the critical dimension and spacing between features cannot be sufficiently reduced, limiting transistor density
Solution Approach 1:
The patent segments the gate patterning process into multiple steps: forming mandrels, depositing spacers, selectively removing gate material in specific regions, and forming endcap structures. This segmentation allows precise control of critical dimensions through spacer thickness rather than relying solely on lithographic resolution, thereby improving manufacturing precision while managing process complexity
Solution Approach 2:
The patent performs preliminary actions by pre-forming spacers and endcap structures before final gate patterning. The spacers are deposited and patterned in advance to define the precise location and dimensions of gate regions, enabling accurate critical dimension control before the actual gate formation occurs
2Productivity
If transistor dimensions are reduced to increase density, then more devices fit on chip, but maintaining mobility improvement and short channel control becomes increasingly difficult
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional gate-all-around structures that wrap around nanowire channels in multiple dimensions. This dimensional change provides superior electrostatic control and short channel effect suppression at scaled dimensions, maintaining reliability while enabling higher transistor density through vertical stacking
Solution Approach 2:
The patent applies different material properties and structural characteristics to specific regions: high-k dielectric materials are used in gate stacks for improved electrostatic control, strain engineering is applied locally in channel regions to maintain carrier mobility, and selective endcap structures are formed at gate ends to optimize electrical characteristics while maintaining short channel control
3Productivity
If narrow poly cuts are formed to increase transistor density, then spacing between features is reduced, but maintaining precise dimensional control becomes more difficult
Solution Approach 1:
The patent employs self-aligned spacer formation where spacers automatically position themselves relative to mandrels and gate structures through conformal deposition. This self-alignment mechanism eliminates the need for separate lithographic alignment steps, enabling precise poly cut dimension control even at narrow widths while increasing transistor density
Solution Approach 2:
The patent controls poly cut dimensions by adjusting spacer deposition thickness and material properties rather than relying on lithographic parameters. By changing the spacer material and deposition conditions, precise dimensional control is achieved independent of lithographic resolution limits, enabling narrow poly cuts with high precision
Data Source
AI summary
Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.