GAA Transistor Dielectric Isolation Layout for Channel Leakage
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing current leakage from channels to the substrate in gate-all-around (GAA) transistor structures, which affects the performance and efficiency of semiconductor devices.
Innovation Solution
The implementation of improved isolation structures, including a sacrificial layer, protection layer, and epitaxial structures, along with specific etching and deposition processes, to form a semiconductor device with reduced parasitic capacitance and enhanced isolation performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional isolation structures are used in GAA transistor structures, then manufacturing is simpler, but current leakage from channels to substrate increases
Solution Approach 1:
The isolation structure is segmented into multiple functional layers: a first isolation layer formed in the substrate, a second isolation layer formed over the first isolation layer and the channel, and a third isolation layer formed over the second isolation layer. This segmentation allows each layer to perform specific isolation functions, effectively reducing current leakage while maintaining manageable complexity through modular design.
Solution Approach 2:
The first isolation layer is formed in the substrate before the channel structure is completely formed, and subsequent isolation layers are formed in sequence as the device structure develops. This preliminary action approach allows the isolation structure to be built incrementally, reducing current leakage from the outset while integrating smoothly with the overall fabrication process.
2Productivity
If geometry size is reduced to increase functional density, then production efficiency increases, but current leakage from channels to substrate worsens
Solution Approach 1:
The isolation structure provides localized electrical isolation precisely where needed - between the channel and the substrate - without affecting other regions of the device. The multi-layer isolation structure is strategically positioned to address current leakage at the channel-substrate interface, enabling continued scaling to increase functional density while maintaining electrical performance through targeted local isolation.
Data Source
AI summary
A device includes a semiconductor substrate, a channel layer, a gate structure, source/drain epitaxial structures, and a dielectric isolation layer. The channel layer is over the semiconductor substrate. The gate structure is over the semiconductor substrate and surrounds the channel layer. The source/drain epitaxial structures are connected to the channel layer and arranged in a first direction. The dielectric isolation layer is between the gate structure and the semiconductor substrate. The dielectric isolation layer is wider than the gate structure but narrower than the channel layer in the first direction.