GAA FET Gate Stack With Thinner Interfacial Layers and Low Leakage
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Solution Overview
Problem
As semiconductor devices transition to sub-20-25 nm technology nodes, gate-all-around FETs require further improvements to address challenges of reduced capacitance equivalent thickness and current leakage while maintaining performance.
Innovation Solution
The thickness of interfacial layers between the gate dielectric layer and the channel regions is reduced, using materials with different lattice constants for the first and second semiconductor layers, and employing a manufacturing process that includes alternating deposition, etching, and formation of nanosheets to enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of interfacial layers is reduced to improve capacitance equivalent thickness, then device performance is improved, but current leakage may increase
Solution Approach 1:
The patent employs a composite interfacial layer structure consisting of multiple layers with different materials (e.g., silicon oxide, silicon nitride, silicon oxynitride) rather than a single uniform layer. This composite structure allows optimization of both thickness and leakage characteristics by combining materials with complementary properties - some layers provide low dielectric constant to reduce capacitance while others provide high barrier properties to prevent current leakage.
Solution Approach 2:
The patent applies different material compositions and thicknesses at different locations and interfaces within the interfacial layer structure. Specifically, different layers are tailored with specific materials and thicknesses to address local requirements - such as having thinner layers where capacitance reduction is critical and thicker or more barrier-oriented layers where leakage prevention is paramount.
2Manufacturing precision
If alternating deposition and etching processes are used to form nanosheets, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the channel structure into multiple discrete nanosheets formed through alternating deposition and etching cycles. Each nanosheet is a separate, precisely-controlled layer with defined thickness and spacing. This segmentation allows independent optimization of each nanosheet's properties and enables precise control over the overall channel characteristics by adjusting the number, thickness, and spacing of individual nanosheets.
Solution Approach 2:
The manufacturing process employs periodic cycles of deposition and etching to build the multi-layer nanosheet structure. Each cycle deposits a thin layer of semiconductor material followed by an etching step that defines the nanosheet geometry. This periodic repetition of standardized cycles enables precise control over nanosheet thickness and spacing while maintaining process scalability and reducing the complexity of designing each layer individually.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces capacitance equivalent thickness without increasing current leakage, thereby improving the performance of GAA FETs by enhancing their operational efficiency and reliability.
Implementation Method 1
A metal silicate layer is formed over the channel region after the metal-containing layer is formed
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming an interfacial layer over a channel region and forming a metal-containing layer over the interfacial layer. A metal silicate layer is formed over the channel region after forming the metal-containing layer. A portion of the metal silicate layer is removed. A gate dielectric layer is formed over the channel region after removing the portion of the metal silicate layer, and a gate electrode layer is formed over the gate dielectric layer.