Recessed Bottom Channel Design for GAA FET Leakage Control
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Solution Overview
Problem
Gate-all-around (GAA) FETs suffer from current leakage at the bottommost portion of the stack of channel layers between doped epitaxial source/drain features, and existing solutions either introduce dopant diffusion issues or compromise other aspects of device fabrication.
Innovation Solution
A method for forming a semiconductor structure that includes a substrate with a top semiconductor layer over an isolation layer, where the top semiconductor layer is recessed to a desired thickness to reduce current leakage, and isolation features are configured as an etching buffer to prevent inadvertent exposure of the bottom semiconductor layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the top semiconductor layer is recessed to reduce current leakage, then current leakage is reduced, but the risk of exposing the bottom semiconductor layer increases
Solution Approach 1:
The patent introduces an isolation layer as an intermediary between the top and bottom semiconductor layers. This isolation layer acts as a buffer that prevents direct exposure of the bottom semiconductor layer during the recessing process, while still allowing the top layer to be recessed sufficiently to reduce current leakage. The isolation layer is specifically designed with thickness and material properties that balance these competing requirements.
Solution Approach 2:
The patent applies preliminary action by forming the isolation layer and configuring isolation features before the recessing process. The isolation features are pre-configured to serve as etching buffers that will prevent over-etching during subsequent processing steps. This preliminary configuration ensures that when the top semiconductor layer is recessed, the bottom layer is protected from exposure.
2Reliability
If existing methods are used to address current leakage, then current leakage is reduced, but dopant diffusion issues or other fabrication compromises occur
Solution Approach 1:
The isolation layer serves as a mediator that enables current leakage reduction without requiring dopant diffusion or other compromising fabrication changes. By providing a physical and electrical isolation mechanism, it allows the top semiconductor layer to be recessed for leakage reduction while maintaining clean interfaces and avoiding dopant contamination issues that would arise from other methods.
Solution Approach 2:
The patent segments the substrate structure into distinct layers: bottom semiconductor layer, isolation layer, and top semiconductor layer. This segmentation allows independent optimization of each layer's function - the bottom layer for device operation, the isolation layer for leakage prevention and process protection, and the top layer for active device formation - thereby avoiding the fabrication compromises associated with unified structure approaches.
Data Source
AI summary
A semiconductor structure includes a substrate including a dielectric layer over a semiconductor layer and an active region protruding from the dielectric layer. The active region includes a stack of semiconductor layers. The semiconductor structure further includes a metal gate structure disposed over the active region and interleaved with the stack of semiconductor layers, an isolation structure over the dielectric layer and covering sidewalls of a bottommost semiconductor layer, and an epitaxial source/drain (S/D) feature disposed adjacent to the metal gate structure. A bottom surface of the epitaxial S/D feature is defined by the bottommost semiconductor layer, and a portion of the bottommost semiconductor layer under the epitaxial S/D feature has a thickness less than a thickness of the dielectric layer.