GAA FET Nanosheet Structure for Higher On-Current Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Challenges exist in optimizing the driving electrical current (on-current) of semiconductor FET devices, particularly in three-dimensional designs like FinFETs and GAA FETs, due to variations in channel region dimensions such as fin height or nano sheet thickness and number.
Innovation Solution
The development of semiconductor devices incorporating two or more types of GAA FETs with different numbers of nano sheets or nano wires, along with a manufacturing method that adjusts channel region dimensions to enhance on-current performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the channel region dimensions (fin height or nano sheet thickness) are increased to enhance on-current, then the driving electrical current improves, but the device density and scaling capability deteriorate
Solution Approach 1:
The channel region is segmented into multiple discrete nano sheets or nano wires instead of a single continuous fin structure. This segmentation allows the total channel width to be distributed across multiple thinner sheets, maintaining high on-current through increased total width while keeping individual sheet thickness small for good vertical field control and scalability.
Solution Approach 2:
The invention transitions from a two-dimensional fin structure to a three-dimensional gate-all-around structure with multiple nano sheets stacked vertically. This dimensional change enables the channel to extend in the vertical dimension, increasing total channel width and on-current without increasing the lateral footprint, thus maintaining device density.
2Power
If the number of nano sheets or wires is increased to improve on-current, then the driving electrical current enhances, but the manufacturing complexity increases
Solution Approach 1:
Multiple nano sheets are merged into a single integrated GAA FET structure under one gate electrode. This merging approach allows multiple channel sheets to be fabricated simultaneously using unified processing steps, reducing manufacturing complexity compared to creating separate devices. The gate-all-around structure envelops all sheets in a single operation.
Solution Approach 2:
The gate-all-around structure serves multiple functions simultaneously: it controls the channel for all nano sheets, provides electrical contact to multiple channels, and acts as a unified control element. This multi-functionality reduces the number of separate components needed, simplifying the overall device architecture and manufacturing process.
3Power
If the fin height or channel width is increased to enhance on-current, then the driving electrical current improves, but the short channel effects worsen
Solution Approach 1:
The gate structure is positioned asymmetrically surrounding the channel from all four sides (gate-all-around), rather than only from the top. This asymmetric 3D configuration creates superior electrostatic control over the channel, effectively suppressing short channel effects even when the channel dimensions are scaled to maintain high on-current.
Solution Approach 2:
The gate-all-around structure acts as an intermediary that mediates between the source/drain regions and the channel. By completely surrounding the channel, the gate provides enhanced control over carrier flow, preventing direct source-drain interaction that causes short channel effects, while still allowing sufficient current flow for high on-current performance.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed over a substrate, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure is etched thereby forming a source/drain space, ends of the first semiconductor layers is laterally etched, an insulating layer is formed on a sidewall of the source/drain space, the insulating layer is partially etched, thereby forming one or more inner spacers on an etched end face of each of one or more first semiconductor layers and leaving a part of the insulating layer as a remaining insulating layer, and a source/drain epitaxial layer is formed in the source/drain space. After the source/drain epitaxial layer is formed, an end face of at least one of the second semiconductor layers is covered by the remaining insulating layer.