GAA FET Source Terminal Layout for Lower SRAM Contact Resistance
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Solution Overview
Problem
Existing technologies for fabricating gate-all-around (GAA) transistors face challenges in reducing contact resistance due to reduced landing area for device-level contacts at smaller technology nodes, particularly at CVSS nodes, which affects processing speed and stability of SRAM cells.
Innovation Solution
The solution involves designing GAA FET structures with enlarged contact landing areas and via sizes in SRAM cells, where the p-type fins have a wider source terminal portion compared to their channel region, increasing the contact area without expanding the overall cell size, and using a method that forms semiconductor fins with varying widths to accommodate larger source contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If GAA transistor structures are used to reduce chip footprint, then device density is improved, but contact landing area is reduced leading to increased contact resistance
Solution Approach 1:
The fin structure is designed with non-uniform width where the source terminal portion is wider than the channel region. This local variation in geometry provides increased contact landing area specifically at the source terminal without increasing the overall device footprint or channel width, thus maintaining high device density while reducing contact resistance.
Solution Approach 2:
The invention utilizes the vertical dimension by creating a three-dimensional gate-all-around structure that wraps around the fin from all sides. This 3D configuration allows the gate to control the channel more effectively while the widened source terminal portion provides additional lateral space for contacts without increasing the planar footprint.
2Reliability
If contact landing area is increased to reduce contact resistance, then reliability is improved, but overall cell size increases
Solution Approach 1:
The fin width is selectively increased only at the source terminal region where contact landing is required, while the channel region maintains its original narrow dimensions. This localized geometric modification provides the necessary contact area without expanding the overall transistor footprint or SRAM cell size.
Solution Approach 2:
The fin structure exhibits asymmetric width distribution along its length, with the source terminal portion being wider than the channel region. This asymmetric design optimizes the structure for both functions: narrow channel for high density and wide source terminal for low contact resistance, without requiring symmetric expansion of the entire device.
Data Source
AI summary
A semiconductor structure includes a first active region and second active region extending lengthwise along a first direction. The first active region includes a first channel region of a first transistor and having a first channel width along a second direction perpendicular to the first direction, a first source/drain terminal of the first transistor and having a first width along the second direction and greater than the first channel width, and a first epitaxial source/drain feature of the first transistor and disposed over the first source/drain terminal. The second active region includes a second channel region of a second transistor and having a second channel width along the second direction, a second source/drain terminal of the second transistor and having a second width along the second direction and greater than the second channel width, and a second epitaxial source/drain feature of the second transistor and over the second source/drain terminal.