GAA Fin Structure Patterning for Higher Integration Density
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Solution Overview
Problem
The semiconductor industry faces challenges in further increasing integration density due to limitations in feature size reduction, which affects device speed and manufacturing costs, as feature sizes approach physical limits.
Innovation Solution
The implementation of a gate all around (GAA) transistor structure manufacturing method involving double-patterning or multi-patterning processes, including the formation of sacrificial layers, spacers, and dielectric walls, allows for the creation of fin structures and channel layers with precise patterning, enabling tighter pitch and higher integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size is continuously reduced to increase integration density, then integration density improves, but manufacturing difficulty increases and device speed deteriorates due to approaching physical limits
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional FinFET structures with vertical channels extending along a first direction and gates wrapping around from multiple directions. This dimensional change enables continued scaling and increased integration density without further reducing lateral feature sizes, thereby avoiding the manufacturing difficulties associated with sub-10nm lithography while maintaining improved device performance through enhanced gate control.
Solution Approach 2:
The patent employs double-patterning or multi-patterning processes that divide the patterning operation into multiple sequential steps, each creating a portion of the final fin structure pattern. This segmentation allows achievement of tighter pitch and higher integration density through staged patterning operations rather than attempting to create all features in a single lithography step, thus managing manufacturing complexity.
2Quantity of substance
If feature size is reduced to increase integration density, then integration density improves, but device speed worsens due to physical limits
Solution Approach 1:
The FinFET structure introduces vertical dimensionality with channels extending in the first direction and gates positioned to control channels from top, bottom, and sidewalls. This three-dimensional architecture provides superior gate control over the channel compared to planar devices, enabling maintained or improved device speed despite reduced feature sizes by preventing short-channel effects and enhancing carrier modulation.
Solution Approach 2:
The gate structure completely surrounds the channel region in a nested configuration, with gates positioned at top, bottom, and sidewalls of the vertical channel. This all-around gate nesting provides comprehensive control of the channel from multiple directions simultaneously, improving device performance and speed by maximizing gate control while maintaining compact footprint for high integration density.
3Quantity of substance
If double-patterning or multi-patterning processes are used to create tighter pitch, then integration density improves, but device complexity increases
Solution Approach 1:
The patent divides the fin structure patterning into multiple sequential patterning steps, where each step creates a subset of the final pattern. This segmentation of the patterning process into manageable stages enables achievement of tighter pitch and higher integration density while controlling process complexity through systematic, repeatable operations rather than attempting complex single-step patterning.
Solution Approach 2:
The double-patterning or multi-patterning approach performs preliminary patterning actions in earlier process steps to establish intermediate patterns that guide subsequent patterning operations. This preliminary action sequence simplifies the overall process by breaking down the complex task of creating tight-pitch fins into preparatory steps followed by final pattern formation, making the manufacturing process more controllable.
Data Source
AI summary
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes first semiconductor channel layers, second semiconductor channel layers, a dielectric wall, a gate structure, a source/drain electrode and an inner spacer. The first semiconductor channel layers are stacked vertically apart along a first direction over a substrate. The second semiconductor channel layers are stacked vertically apart along the first direction over the substrate. The dielectric wall is disposed between and separates the first semiconductor channel layers and the second first semiconductor channel layers, wherein the dielectric wall comprises a liner and a dielectric wall material disposed over the liner. The gate structure extends along a second direction perpendicular to the first direction disposed crossing over a channel region of the first fin structure and a channel region of the second fin structure. The source/drain electrode is in contact with the first semiconductor channel layers. The inner spacer is enclosed by the first semiconductor channel layers, the gate structure, the dielectric wall and the source/drain electrode, wherein the inner spacer is in contact with the dielectric wall material of the dielectric wall.