GAA Floating-Gate Memory Cell Layout for Low-Voltage Erase
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in designing high-density three-dimensional non-volatile memory devices, such as vertical NAND memory strings, due to the need for efficient programming, reading, and erasing operations while maintaining reliability and reducing voltage requirements.
Innovation Solution
The proposed solution involves a semiconductor device configuration with a gate all around (GAA) transistor structure, including a floating gate, control gate, and an erase gate, where the erase gate is strategically placed between memory cells to facilitate efficient charge storage and erasure, and the use of specific voltage ranges for programming, reading, and erasing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional flash memory cell structures are used, then manufacturing processes are simpler, but memory array density and functional integration are limited
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell layouts to three-dimensional vertical memory structures. Memory cells are stacked vertically with tunneling gates wrapping around channel regions, enabling significant increases in memory density without proportionally increasing footprint area. This dimensional transition allows multiple memory cells to occupy the same lateral space by utilizing the vertical dimension.
Solution Approach 2:
The patent implements nested gate structures where tunneling gates are positioned within and around channel regions. Control gates are stacked above memory cells, and select gates are integrated into the vertical structure. This nesting arrangement allows multiple functional elements to occupy overlapping or adjacent spatial regions, maximizing the use of available three-dimensional space while maintaining electrical isolation and functional independence.
2Quantity of substance
If higher memory density is achieved through scaling, then array capacity increases, but voltage requirements and interference between adjacent cells increase
Solution Approach 1:
The patent introduces control gates as intermediary elements positioned between adjacent memory cells and floating gates. These control gates act as shielding structures that electrically isolate adjacent floating gates from each other, preventing charge interference and crosstalk. The control gates can be independently biased to create potential barriers that block unwanted electric field interactions between neighboring memory cells, enabling higher density arrangements without compromising signal integrity.
3Quantity of substance
If more memory cells are integrated per chip area, then functional density increases, but programming and erasing operations become less efficient
Solution Approach 1:
The patent implements shared control gate structures that can simultaneously or sequentially control multiple memory cells stacked vertically. A single control gate line can address and operate on multiple memory cells at different vertical levels, reducing the number of independent control lines required. This multi-functional approach allows efficient programming and erasing operations across densely packed three-dimensional memory arrays without proportionally increasing control circuit complexity.
Solution Approach 2:
The patent divides memory arrays into multiple sectors or blocks that can be independently accessed and operated. Each segment can be programmed or erased independently through selective gating, allowing parallel operations on different memory regions. This segmentation enables efficient memory management where only the required portions of the memory array need to be accessed during programming or erasing operations, improving overall productivity in high-density configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory cell reliability, reduces voltage requirements, and improves read current detection, while minimizing interference between adjacent floating gates, thereby improving the overall performance and endurance of the memory devices.
Implementation Method 1
Each memory cell includes a floating gate, a control gate, and a tunneling gate between the floating gate and a channel region
Implementation Method 2
The blocking layer has a first portion between the floating gate and the control gate and a second portion between the tunneling gate and the channel region
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a first semiconductor layer, a first floating gate electrode, a first control gate electrode, an erase gate electrode, and a blocking layer. The semiconductor substrate has a first source/drain region. The first semiconductor layer extends upward from the first source/drain region of the semiconductor substrate. The first floating gate electrode surrounds the first semiconductor layer. The first control gate electrode surrounds the first floating gate electrode and the first semiconductor layer. The erase gate electrode is over the first floating gate electrode and the first control gate electrode. The erase gate electrode surrounds the first semiconductor layer. The blocking layer has a first portion between the first floating gate electrode and the first control gate electrode and a second portion between the erase gate electrode and the first semiconductor layer.