GAA Semiconductor Structure With Thick Gate Dielectric Integration
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Solution Overview
Problem
The integration of gate-all-around (GAA) transistors in semiconductor manufacturing is challenging due to difficulties in forming input/output transistors with a gate dielectric layer of sufficient effective oxide thickness, which is crucial for nanostructure devices.
Innovation Solution
The integration of input/output transistors is achieved by utilizing the lower fin element of a fin structure as a gate electrode layer and replacing the lowermost first semiconductor layer with a gate dielectric layer, ensuring a great effective thickness, and incorporating a multi-patterning process to form the GAA structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional multi-patterning processes are used to form GAA structures, then device scaling and gate control are improved, but manufacturing complexity and difficulty in forming input/output transistors increase
Solution Approach 1:
The manufacturing process is divided into separate stages: first forming the fin structure with initial patterns, then using spacer formation and selective removal to create the final GAA structure. This segmentation allows complex structures to be built from simpler intermediate stages, improving manufacturability while maintaining precision
Solution Approach 2:
The fin structure is formed in advance with specific layers (including the lower fin element that will become the gate electrode) before the actual GAA transistor formation. This preliminary structuring simplifies subsequent steps and enables the integration of input/output transistors with adequate gate dielectric thickness
2Reliability
If the lowermost first semiconductor layer is replaced with a gate dielectric layer to ensure sufficient effective oxide thickness, then input/output transistor performance is improved, but the manufacturing process becomes more challenging
Solution Approach 1:
The lower fin element serves dual purposes: it forms part of the fin structure during initial fabrication and subsequently becomes the gate electrode layer for input/output transistors. This multi-functionality eliminates the need for separate gate electrode formation steps, simplifying the overall process while ensuring adequate gate dielectric thickness
Solution Approach 2:
The fin structure's lower fin element automatically serves as the gate electrode material source, requiring only selective removal of the lowermost semiconductor layer and formation of gate dielectric on the exposed fin surface. The structure essentially configures itself for the next functional stage without requiring complex additional processing
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a fin element extending lengthwise along a first direction, a plurality of nanostructures over the fin element, an isolation structure surrounding the fin element, and a first source/drain feature and a second source/drain feature on the isolation structure and bordering the plurality of nanostructures. The first source/drain feature, the plurality of nanostructures and the second source/drain feature are sequentially arranged along a second direction that is different from the first direction.