GAA Gate Isolation Structure for Tighter Fin Spacing
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Solution Overview
Problem
In advanced semiconductor technology nodes, the scaling of gate-all-around (GAA) transistor devices is constrained by layout restrictions due to spacing limitations between gate isolation structures and neighboring semiconductor fins, which hinders further miniaturization and increases manufacturing complexity.
Innovation Solution
A self-aligned fabrication process is employed to form inactive fin structures and gate isolation structures, allowing for reduced physical separation between adjacent GAA devices and improved spacing constraints, enabling more compact device design and enhanced manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional fabrication processes are used for GAA devices, then manufacturing reliability is maintained, but physical separation between devices cannot be reduced, increasing device area and reducing functional density
Solution Approach 1:
The gate isolation structure is formed before the gate electrode deposition step, establishing the isolation regions in advance. This preliminary action defines the precise locations where gate electrodes will be deposited, enabling reduced spacing between adjacent GAA devices while maintaining manufacturing control and reliability
Solution Approach 2:
The gate isolation structure serves as an intermediary element between adjacent semiconductor fins and gate electrodes. This isolation structure enables precise spatial separation, allowing devices to be placed closer together while maintaining proper electrical isolation and manufacturing precision
2Productivity
If spacing between gate isolation structures and semiconductor fins is reduced, then functional density increases, but manufacturing complexity increases due to tighter tolerances
Solution Approach 1:
By forming gate isolation structures before gate electrode deposition, the patent establishes precise isolation regions in advance. This preliminary positioning simplifies subsequent processing steps and enables reduced spacing between devices without proportionally increasing manufacturing complexity
Solution Approach 2:
The gate isolation structure automatically defines the spacing and positioning for adjacent gate electrodes. This self-aligning approach reduces the need for additional alignment steps and complex processing controls, enabling higher functional density without linearly increasing processing complexity
Data Source
AI summary
A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, and a third semiconductor channel over the substrate and laterally offset from the second semiconductor channel. A first gate structure, a second gate structure, and a third gate structure are over and lateral surround the first, second, and third semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure, and a second inactive fin is between the second gate structure and the third gate structure. A bridge conductor layer is over the first, second, and third gate structures, and the first and second inactive fins. A dielectric plug extends from an upper surface of the second inactive fin, through the bridge conductor layer, to at least an upper surface of the bridge conductor layer.